[toolchain-commits] [1610] trunk/gcc-3.4/gcc: * rtl.def (SS_ABS): Fix error in last change.

Mon, 30 Apr 2007 04:09:50 -0700

Title: [1610] trunk/gcc-3.4/gcc: * rtl.def (SS_ABS): Fix error in last change.
Revision
1610
Author
bernds
Date
2007-04-30 04:04:52 -0500 (Mon, 30 Apr 2007)

Log Message

	* rtl.def (SS_ABS): Fix error in last change.
	* config/bfin/bfin.c (reg_or_const_int_operand): New function.
	* config/bfin/bfin.h (PREDICATE_CODES): Add it.
	* config/bfin/bfin.md (flag_mul_macv2hi_parts_acconly_andcc0): Moved
	to proper place after patch got misapplied.


Modified Paths

Diff

Modified: trunk/gcc-3.4/gcc/ChangeLog.bfin (1609 => 1610)


--- trunk/gcc-3.4/gcc/ChangeLog.bfin	2007-04-29 11:43:28 UTC (rev 1609)
+++ trunk/gcc-3.4/gcc/ChangeLog.bfin	2007-04-30 09:04:52 UTC (rev 1610)
@@ -1,3 +1,11 @@
+2007-04-29  Bernd Schmidt  <[EMAIL PROTECTED]>
+
+	* rtl.def (SS_ABS): Fix error in last change.
+	* config/bfin/bfin.c (reg_or_const_int_operand): New function.
+	* config/bfin/bfin.h (PREDICATE_CODES): Add it.
+	* config/bfin/bfin.md (flag_mul_macv2hi_parts_acconly_andcc0): Moved
+	to proper place after patch got misapplied.
+
 2007-04-28  Bernd Schmidt  <[EMAIL PROTECTED]>
 
 	* rtl.def (SS_ABS): New code.

Modified: trunk/gcc-3.4/gcc/config/bfin/bfin.c (1609 => 1610)


--- trunk/gcc-3.4/gcc/config/bfin/bfin.c	2007-04-29 11:43:28 UTC (rev 1609)
+++ trunk/gcc-3.4/gcc/config/bfin/bfin.c	2007-04-30 09:04:52 UTC (rev 1610)
@@ -1831,6 +1831,15 @@
   return 0;
 }
 
+int
+reg_or_const_int_operand (rtx op, enum machine_mode mode)
+{
+  if (GET_CODE (op) == CONST_INT)
+    return true;
+
+  return register_operand (op, mode);
+}
+
 /* Return nonzero if OP is a constant that consists of two parts; lower
    bits all zero and upper bits all ones.  In this case, we can perform
    an AND operation with a sequence of two shifts.  Don't return nonzero

Modified: trunk/gcc-3.4/gcc/config/bfin/bfin.h (1609 => 1610)


--- trunk/gcc-3.4/gcc/config/bfin/bfin.h	2007-04-29 11:43:28 UTC (rev 1609)
+++ trunk/gcc-3.4/gcc/config/bfin/bfin.h	2007-04-30 09:04:52 UTC (rev 1610)
@@ -1192,6 +1192,7 @@
       {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, LABEL_REF}},		\
   {"scale_by_operand", {CONST_INT}},					\
   {"pos_scale_operand", {CONST_INT}},                                  	\
+  {"reg_or_const_int_operand", {SUBREG, REG, ADDRESSOF, CONST_INT}},	\
   {"positive_immediate_operand", {CONST_INT}},				\
   {"reg_or_7bit_operand", {CONST_INT, SUBREG, REG, ADDRESSOF}},		\
   {"reg_or_neg7bit_operand", {CONST_INT, SUBREG, REG, ADDRESSOF}},	\

Modified: trunk/gcc-3.4/gcc/config/bfin/bfin.md (1609 => 1610)


--- trunk/gcc-3.4/gcc/config/bfin/bfin.md	2007-04-29 11:43:28 UTC (rev 1609)
+++ trunk/gcc-3.4/gcc/config/bfin/bfin.md	2007-04-30 09:04:52 UTC (rev 1610)
@@ -2132,70 +2132,6 @@
 			 operands[1], const0_rtx);
 })
 
-;; Same as above, but and CC with the overflow bit generated by the first
-;; multiplication.
-(define_insn "flag_mul_macv2hi_parts_acconly_andcc0"
-  [(set (match_operand:PDI 0 "register_operand" "=B,e,e")
-	(unspec:PDI [(vec_select:HI
-		      (match_operand:V2HI 2 "register_operand" "d,d,d")
-		      (parallel [(match_operand 4 "const01_operand" "P0P1,P0P1,P0P1")]))
-		     (vec_select:HI
-		      (match_operand:V2HI 3 "register_operand" "d,d,d")
-		      (parallel [(match_operand 6 "const01_operand" "P0P1,P0P1,P0P1")]))
-		     (match_operand 10 "const_int_operand" "PB,PA,PA")]
-		    UNSPEC_MUL_WITH_FLAG))
-   (set (match_operand:PDI 1 "register_operand" "=B,e,e")
-	(unspec:PDI [(vec_select:HI
-		      (match_dup 2)
-		      (parallel [(match_operand 5 "const01_operand" "P0P1,P0P1,P0P1")]))
-		     (vec_select:HI
-		      (match_dup 3)
-		      (parallel [(match_operand 7 "const01_operand" "P0P1,P0P1,P0P1")]))
-		     (match_operand:PDI 8 "register_operand" "1,1,1")
-		     (match_operand 9 "const01_operand" "P0P1,P0P1,P0P1")
-		     (match_operand 11 "const_int_operand" "PA,PB,PA")]
-		    UNSPEC_MAC_WITH_FLAG))
-   (set (reg:BI REG_CC)
-	(and:BI (reg:BI REG_CC)
-		(unspec:BI [(vec_select:HI (match_dup 2) (parallel [(match_dup 4)]))
-			    (vec_select:HI (match_dup 3) (parallel [(match_dup 6)]))
-			    (match_dup 10)]
-			   UNSPEC_MUL_WITH_FLAG)))]
-  "MACFLAGS_MATCH_P (INTVAL (operands[10]), INTVAL (operands[11]))"
-{
-  rtx xops[6];
-  const char *templates[] = {
-    "%0 = %h2 * %h3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;",
-    "%0 = %d2 * %h3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;",
-    "%0 = %h2 * %h3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;",
-    "%0 = %d2 * %h3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;",
-    "%0 = %h2 * %d3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;",
-    "%0 = %d2 * %d3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;",
-    "%0 = %h2 * %d3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;",
-    "%0 = %d2 * %d3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;",
-    "%0 = %h2 * %h3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;",
-    "%0 = %d2 * %h3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;",
-    "%0 = %h2 * %h3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;",
-    "%0 = %d2 * %h3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;",
-    "%0 = %h2 * %d3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;",
-    "%0 = %d2 * %d3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;",
-    "%0 = %h2 * %d3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;",
-    "%0 = %d2 * %d3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;" };
-  int alt = (INTVAL (operands[4]) + (INTVAL (operands[5]) << 1)
-	     + (INTVAL (operands[6]) << 2)  + (INTVAL (operands[7]) << 3));
-  xops[0] = operands[0];
-  xops[1] = operands[1];
-  xops[2] = operands[2];
-  xops[3] = operands[3];
-  xops[4] = operands[9];
-  xops[5] = which_alternative == 0 ? operands[10] : operands[11];
-  output_asm_insn (templates[alt], xops);
-  return "";
-}
-  [(set_attr "type" "misc")
-   (set_attr "length" "6")
-   (set_attr "seq_insns" "multi")])
-
 (define_expand "bge"
   [(set (match_dup 1) (match_dup 2))
    (set (pc)
@@ -3334,6 +3270,68 @@
 }
   [(set_attr "type" "dsp32")])
 
+;; Same as above, but and CC with the overflow bit generated by the first
+;; multiplication.
+(define_insn "flag_mul_macv2hi_parts_acconly_andcc0"
+  [(set (match_operand:PDI 0 "register_operand" "=B,e,e")
+	(unspec:PDI [(vec_select:HI
+		      (match_operand:V2HI 2 "register_operand" "d,d,d")
+		      (parallel [(match_operand 4 "const01_operand" "P0P1,P0P1,P0P1")]))
+		     (vec_select:HI
+		      (match_operand:V2HI 3 "register_operand" "d,d,d")
+		      (parallel [(match_operand 6 "const01_operand" "P0P1,P0P1,P0P1")]))
+		     (match_operand 10 "const_int_operand" "PB,PA,PA")]
+		    UNSPEC_MUL_WITH_FLAG))
+   (set (match_operand:PDI 1 "register_operand" "=B,e,e")
+	(unspec:PDI [(vec_select:HI
+		      (match_dup 2)
+		      (parallel [(match_operand 5 "const01_operand" "P0P1,P0P1,P0P1")]))
+		     (vec_select:HI
+		      (match_dup 3)
+		      (parallel [(match_operand 7 "const01_operand" "P0P1,P0P1,P0P1")]))
+		     (match_operand:PDI 8 "register_operand" "1,1,1")
+		     (match_operand 9 "const01_operand" "P0P1,P0P1,P0P1")
+		     (match_operand 11 "const_int_operand" "PA,PB,PA")]
+		    UNSPEC_MAC_WITH_FLAG))
+   (set (reg:BI REG_CC)
+	(and:BI (reg:BI REG_CC)
+		(unspec:BI [(vec_select:HI (match_dup 2) (parallel [(match_dup 4)]))
+			    (vec_select:HI (match_dup 3) (parallel [(match_dup 6)]))
+			    (match_dup 10)]
+			   UNSPEC_MUL_WITH_FLAG)))]
+  "MACFLAGS_MATCH_P (INTVAL (operands[10]), INTVAL (operands[11]))"
+{
+  rtx xops[6];
+  const char *templates[] = {
+    "%0 = %h2 * %h3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;",
+    "%0 = %d2 * %h3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;",
+    "%0 = %h2 * %h3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;",
+    "%0 = %d2 * %h3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;",
+    "%0 = %h2 * %d3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;",
+    "%0 = %d2 * %d3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;",
+    "%0 = %h2 * %d3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;",
+    "%0 = %d2 * %d3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;",
+    "%0 = %h2 * %h3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;",
+    "%0 = %d2 * %h3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;",
+    "%0 = %h2 * %h3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;",
+    "%0 = %d2 * %h3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;",
+    "%0 = %h2 * %d3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;",
+    "%0 = %d2 * %d3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;",
+    "%0 = %h2 * %d3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;",
+    "%0 = %d2 * %d3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;" };
+  int alt = (INTVAL (operands[4]) + (INTVAL (operands[5]) << 1)
+	     + (INTVAL (operands[6]) << 2)  + (INTVAL (operands[7]) << 3));
+  xops[0] = operands[0];
+  xops[1] = operands[1];
+  xops[2] = operands[2];
+  xops[3] = operands[3];
+  xops[4] = operands[9];
+  xops[5] = which_alternative == 0 ? operands[10] : operands[11];
+  output_asm_insn (templates[alt], xops);
+  return "";
+}
+  [(set_attr "type" "misc")
+   (set_attr "length" "6")])
 
 (define_insn "mulhisi_ll"
   [(set (match_operand:SI 0 "register_operand" "=d")

Modified: trunk/gcc-3.4/gcc/rtl.def (1609 => 1610)


--- trunk/gcc-3.4/gcc/rtl.def	2007-04-29 11:43:28 UTC (rev 1609)
+++ trunk/gcc-3.4/gcc/rtl.def	2007-04-30 09:04:52 UTC (rev 1610)
@@ -1210,7 +1210,7 @@
 DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", '1')
 
 /* Absolute value with signed saturation.  */
-DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY)
+DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", '1')
 
 /* Shift left with signed saturation.  */
 DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", '2')

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