The SRD0_PFC0 register was not configured correctly to enable the GPIO's
49-63 for GPIO. They have been configured as trace signals. This patch
fixes this by clearing the corresponding bit.
Signed-off-by: Stefan Roese <[EMAIL PROTECTED]>
---
board/pcs440ep/pcs440ep.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c
index 90e99d3..96adbc9 100644
--- a/board/pcs440ep/pcs440ep.c
+++ b/board/pcs440ep/pcs440ep.c
@@ -175,7 +175,7 @@ int board_early_init_f(void)
*-------------------------------------------------------------------*/
mfsdr(sdr_pci0, reg);
mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
- mtsdr(sdr_pfc0, 0x00000100); /* Pin function: enable GPIO49-63 */
+ mtsdr(sdr_pfc0, 0x00000000); /* Pin function: enable GPIO49-63 */
mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins,
select IRQ5 */
return 0;
--
1.5.4.rc5
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