On 16:14 Thu 12 Jun , Antonio R. Costa wrote:
>
> Signed-off-by: Antonio R. Costa <[EMAIL PROTECTED]>
>
> diff --git a/include/asm-arm/arch-at572d940hf/at572d940hf.h
> b/include/asm-arm/arch-at572d940hf/at572d940hf.h
> new file mode 100644
> index 0000000..53f049b
> --- /dev/null
> +++ b/include/asm-arm/arch-at572d940hf/at572d940hf.h
> @@ -0,0 +1,147 @@
> +/*
> + * include/asm-arm/arch-at91/AT572D940HFhf.h
> + *
> + * (C) 2008 Antonio R. Costa
> + *
> + * Common definitions.
> + * Based on AT572D940HFHF datasheet rev A.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef AT572D940HFHF_H
> +#define AT572D940HFHF_H
> +
> +/*
> + * Peripheral identifiers/interrupts.
> + */
> +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
> +#define AT91_ID_SYS 1 /* System Peripherals */
> +#define AT572D940HF_ID_PIOA 2 /* Parallel IO Controller A */
> +#define AT572D940HF_ID_PIOB 3 /* Parallel IO Controller B */
> +#define AT572D940HF_ID_PIOC 4 /* Parallel IO Controller C */
> +#define AT572D940HF_ID_EMAC 5 /* Ethernet */
> +#define AT572D940HF_ID_US0 6 /* USART 0 */
> +#define AT572D940HF_ID_US1 7 /* USART 1 */
> +#define AT572D940HF_ID_US2 8 /* USART 2 */
> +#define AT572D940HF_ID_MCI 9 /* Multimedia Card Interface */
> +#define AT572D940HF_ID_UDP 10 /* USB Device Port */
> +#define AT572D940HF_ID_TWI 11 /* Two-Wire Interface */
> +#define AT572D940HF_ID_TWI0 11 /* Two-Wire Interface */
> +#define AT572D940HF_ID_SPI0 12 /* Serial Peripheral Interface 0 */
> +#define AT572D940HF_ID_SPI1 13 /* Serial Peripheral Interface 1 */
> +#define AT572D940HF_ID_SSC 14 /* Serial Synchronous Controller */
> +#define AT572D940HF_ID_SSC0 14 /* Serial Synchronous Controller */
> +#define AT572D940HF_ID_SSC1 15 /* Serial Synchronous Controller */
> +#define AT572D940HF_ID_SSC2 16 /* Serial Synchronous Controller */
> +#define AT572D940HF_ID_TC0 17 /* Timer Counter 0 */
> +#define AT572D940HF_ID_TC1 18 /* Timer Counter 1 */
> +#define AT572D940HF_ID_TC2 19 /* Timer Counter 2 */
> +#define AT572D940HF_ID_UHP 20 /* USB Host port */
> +#define AT572D940HF_ID_SSC3 21 /* Serial Synchronous Controller */
> +#define AT572D940HF_ID_TWI1 22 /* Two-Wire Interface */
> +#define AT572D940HF_ID_CAN0 23 /* CAN Controller */
> +#define AT572D940HF_ID_CAN1 24 /* CAN Controller */
> +#define AT572D940HF_ID_mHALT 25 /* mAgicV DSP halt int */
> +#define AT572D940HF_ID_mSIRQ1 26 /* mAgicV DSP SIRQ1 int */
> +#define AT572D940HF_ID_mEXC 27 /* mAgicV DSP Exception int */
> +#define AT572D940HF_ID_mEDMA 28 /* mAgicV DSP end of DMA transfer int */
> +#define AT572D940HF_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
> +#define AT572D940HF_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
> +#define AT572D940HF_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
> +
> +#define AT91_ID_US0 AT572D940HF_ID_US0
> +#define AT91_ID_US1 AT572D940HF_ID_US1
> +#define AT91_ID_US2 AT572D940HF_ID_US2
> +#define AT91_ID_US3 AT572D940HF_ID_US3
few whitespaces
> +
> +#define AT91_ID_UHP AT572D940HF_ID_UHP
> +#define AT91_PMC_UHP AT572D940HF_ID_UHP
> +
> +/*
> + * User Peripheral physical base addresses.
> + */
> +#define AT572D940HF_BASE_TCB0 0xfffa0000
> +#define AT572D940HF_BASE_TC0 0xfffa0000
> +#define AT572D940HF_BASE_TC1 0xfffa0040
> +#define AT572D940HF_BASE_TC2 0xfffa0080
> +#define AT572D940HF_BASE_UDP 0xfffa4000
> +#define AT572D940HF_BASE_MCI 0xfffa8000
> +#define AT572D940HF_BASE_TWI 0xfffac000
> +#define AT572D940HF_BASE_US0 0xfffb0000
> +#define AT572D940HF_BASE_US1 0xfffb4000
> +#define AT572D940HF_BASE_US2 0xfffb8000
> +#define AT572D940HF_BASE_SSC 0xfffbc000
> +#define AT572D940HF_BASE_ISI 0xfffc0000
> +#define AT572D940HF_BASE_EMAC 0xfffd8000
> +#define AT572D940HF_BASE_SPI0 0xfffc8000
> +#define AT572D940HF_BASE_SPI1 0xfffcc000
> +#define AT572D940HF_BASE_US3 0xfffd0000
> +#define AT572D940HF_BASE_US4 0xfffd4000
> +#define AT572D940HF_BASE_US5 0xfffd8000
> +#define AT572D940HF_BASE_TCB1 0xfffdc000
> +#define AT572D940HF_BASE_TC3 0xfffdc000
> +#define AT572D940HF_BASE_TC4 0xfffdc040
> +#define AT572D940HF_BASE_TC5 0xfffdc080
> +#define AT572D940HF_BASE_ADC 0xfffe0000
> +#define AT572D940HF_BASE_RSTC 0xfffffd00
> +#define AT91_BASE_SYS 0xffffea00
> +
> +#define AT91_BASE_EMAC AT572D940HF_BASE_EMAC
> +#define AT91_BASE_SPI AT572D940HF_BASE_SPI0
> +#define MMCI_BASE AT572D940HF_BASE_MCI
> +
> +/*
> + * System Peripherals (offset from AT91_BASE_SYS)
> + */
> +#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
> +#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
> +#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
> +#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
> +#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
> +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
> +#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
> +#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
> +#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
> +#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
> +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
> +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
> +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
> +#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
> +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
> +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
> +#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
> +
> +#define AT91_USART0 AT572D940HF_BASE_US0
> +#define AT91_USART1 AT572D940HF_BASE_US1
> +#define AT91_USART2 AT572D940HF_BASE_US2
> +#define AT91_USART3 AT572D940HF_BASE_US3
> +#define AT91_USART4 AT572D940HF_BASE_US4
> +#define AT91_USART5 AT572D940HF_BASE_US5
> +
> +/*
> + * Internal Memory.
> + */
> +#define AT572D940HF_ROM_BASE 0x00400000 /* Internal ROM base address */
> +#define AT572D940HF_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
> +
> +#define AT572D940HF_SRAM0_BASE 0x00100000 /* Internal SRAM 0 base
> address */
> +#define AT572D940HF_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size
> (4Kb) */
> +#define AT572D940HF_SRAM1_BASE 0x00200000 /* Internal SRAM 0 base
> address */
> +#define AT572D940HF_SRAM1_SIZE SZ_16K /* Internal SRAM 0 size
> (4Kb) */
> +#define AT572D940HF_SRAM2_BASE 0x00300000 /* Internal SRAM 1 base
> address */
> +#define AT572D940HF_SRAM2_SIZE SZ_16K /* Internal SRAM 1 size
> (4Kb) */
> +
> +//SDRAM
No c++ comment please
> +#define AT572D940HF_SDRAM_BASE 0x20000000
> +
> +// USB Host
No c++ comment please
> +#define AT572D940HF_UHP_BASE 0x00500000 /* USB Host controller */
> +
> +#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base
> address */
> +#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
> +
> +#endif
> diff --git a/include/asm-arm/arch-at572d940hf/at572d940hf_matrix.h
> b/include/asm-arm/arch-at572d940hf/at572d940hf_matrix.h
> new file mode 100644
> index 0000000..a8e9fec
> --- /dev/null
> +++ b/include/asm-arm/arch-at572d940hf/at572d940hf_matrix.h
> @@ -0,0 +1,78 @@
> +/*
Please adapt this file for your the at572d940hf or if its really the
same include the at91sam9260_matrix.h
> + * include/asm-arm/arch-at91/at91sam9260_matrix.h
> + *
> + * Memory Controllers (MATRIX, EBI) - System peripherals registers.
> + * Based on AT91SAM9260 datasheet revision B.
> + *
> diff --git a/include/asm-arm/arch-at572d940hf/at572d940hf_mc.h
> b/include/asm-arm/arch-at572d940hf/at572d940hf_mc.h
> new file mode 100644
> index 0000000..161d504
> --- /dev/null
> +++ b/include/asm-arm/arch-at572d940hf/at572d940hf_mc.h
> @@ -0,0 +1,140 @@
> +/*
Please adapt this file for your the at572d940hf or if its really the
same include the at91sam926x_mc.h
> + * include/asm-arm/arch-at91/at91sam926x_mc.h
> + *
> + * Memory Controllers (SMC, SDRAMC) - System peripherals registers.
> + * Based on AT91SAM9261 datasheet revision D.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> diff --git a/include/asm-arm/arch-at572d940hf/interrupts.h
> b/include/asm-arm/arch-at572d940hf/interrupts.h
> new file mode 100644
> index 0000000..71d3f5d
> --- /dev/null
> +++ b/include/asm-arm/arch-at572d940hf/interrupts.h
> @@ -0,0 +1,41 @@
> +/*
> + * include/asm-arm/arch-at572d940/at91_aic.h
> + *
> + * Copyright (C) 2008 Antonio R. Costa
> + * Copyright (C) ATMEL
> + *
> + * Advanced Interrupt Controller (AIC).
> + * Based on AT572D940 datasheet.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef __AT572D940_INTERRUPTS_H__
> +#define __AT572D940_INTERRUPTS_H__
> +
> +#include <asm/arch/at91_aic.h>
> +
> +typedef void (*irq_handler_t) (unsigned long int);
> +
some coding style issue
> +#define SET_IRQ_HANDLER(s,m,h) \
> +do { \
> + AIC_WRITE(AIC_SMR(s),m); \
> + AIC_WRITE(AIC_SVR(s),h); \
> + AIC_WRITE(AIC_IECR,(1<<s)); \
> +} while(0)
> +
> +#define RESET_IRQ_HANDLER(s) \
> +do { \
> + AIC_WRITE(AIC_SMR(s),0); \
> + AIC_WRITE(AIC_SVR(s),0); \
> + AIC_WRITE(AIC_IDCR,(1<<s)); \
> +} while(0)
> +
> +#define IRQ_ACKNOWLEDGE(n) AIC_WRITE(AIC_EOICR,(n))
> +
> +extern reset_irqs(void);
> +
Best Regards,
J.
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