This patch adds the CONFIG_SKIP_LOWLEVEL_INIT option to start.S. This
enables support for boards where the lowlevel initialization is
already done when U-Boot runs (e.g. via OnChip ROM).
Also the data cache will be flushed upon relocation. This is missing
in the current implementation.
All this will be used in the upcoming VCTH board support.
Signed-off-by: Stefan Roese <[EMAIL PROTECTED]>
---
cpu/mips/start.S | 19 ++++++++++++++++++-
1 files changed, 18 insertions(+), 1 deletions(-)
diff --git a/cpu/mips/start.S b/cpu/mips/start.S
index 6a22302..5b71b00 100644
--- a/cpu/mips/start.S
+++ b/cpu/mips/start.S
@@ -243,9 +243,11 @@ reset:
mtc0 zero, CP0_COUNT
mtc0 zero, CP0_COMPARE
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT)
/* CONFIG0 register */
li t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
+#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
/* Initialize $gp.
*/
@@ -255,6 +257,7 @@ reset:
1:
lw gp, 0(ra)
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT)
/* Initialize any external memory.
*/
la t9, lowlevel_init
@@ -271,6 +274,7 @@ reset:
*/
li t0, CONF_CM_CACHABLE_NONCOHERENT
mtc0 t0, CP0_CONFIG
+#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
/* Set up temporary stack.
*/
@@ -323,6 +327,14 @@ relocate_code:
* t1 = target address
* t2 = source end address
*/
+
+ /*
+ * Save destination address and size for later usage in flush_cache()
+ */
+ move t7, a1 /* save gd in t7 */
+ move a0, t1 /* a0 <-- destination addr */
+ sub a1, t2, t0 /* a1 <-- size */
+
/* On the purple board we copy the code earlier in a special way
* in order to solve flash problems
*/
@@ -338,6 +350,11 @@ relocate_code:
/* If caches were enabled, we would have to flush them here.
*/
+ /* a0 & a1 are already set up for flush_cache(start, size) */
+ la t9, flush_cache
+ jalr t9
+ nop
+
/* Jump to where we've relocated ourselves.
*/
addi t0, a2, in_ram - _start
@@ -387,7 +404,7 @@ in_ram:
bltl t1, t2, 1b
sw zero, 0(t1) /* delay slot */
- move a0, a1
+ move a0, t7 /* a0 <-- gd */
la t9, board_init_r
jr t9
move a1, a2 /* delay slot */
--
1.6.0.4
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