1. rd_to_pre is missed to add the AL.
2. add the support of DDR2-533,667,800 DIMMs
3. cpo
4. make the AL to min to gain better performance.
The Micron MT9HTF6472CHY-667D1 DIMMs test passed on
MPC837xEMDS platform at 266MHz/333MHz/400MHz data rate.
Reported-by: Joakim Tjernlund <joakim.tjernl...@transmode.se>
Signed-off-by: Dave Liu <dave...@freescale.com>
---
cpu/mpc83xx/spd_sdram.c | 23 ++++++++++++++++++++---
1 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 42a4e67..ecbc70c 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -319,7 +319,21 @@ long int spd_sdram()
ddrc_clk = gd->mem_clk / 1000000;
effective_data_rate = 0;
- if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
+ if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */
+ if (spd.cas_lat & 0x08)
+ caslat = 3;
+ else
+ caslat = 4;
+
+ if (ddrc_clk <= 460 && ddrc_clk > 350)
+ effective_data_rate = 400;
+ else if (ddrc_clk <=350 && ddrc_clk > 280)
+ effective_data_rate = 333;
+ else if (ddrc_clk <= 280 && ddrc_clk > 230)
+ effective_data_rate = 266;
+ else
+ effective_data_rate = 200;
+ } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR
400 */
if (ddrc_clk <= 460 && ddrc_clk > 350) {
/* DDR controller clk at 350~460 */
effective_data_rate = 400; /* 5ns */
@@ -529,7 +543,7 @@ long int spd_sdram()
if (spd.mem_type == SPD_MEMTYPE_DDR2
&& (odt_wr_cfg || odt_rd_cfg)
&& (caslat < 4)) {
- add_lat = trcd_clk - 1;
+ add_lat = 4 - caslat;
if ((add_lat + caslat) < 4) {
add_lat = 0;
}
@@ -566,6 +580,7 @@ long int spd_sdram()
/* Convert SPD value from quarter nanos to picos. */
trtp_clk = picos_to_clk(spd.trtp * 250);
+ trtp_clk += add_lat;
cke_min_clk = 3; /* By the book. */
four_act = picos_to_clk(37500); /* By the book. 1k pages? */
@@ -579,7 +594,9 @@ long int spd_sdram()
if (spd.mem_type == SPD_MEMTYPE_DDR2) {
if (effective_data_rate == 266) {
cpo = 0x4; /* READ_LAT + 1/2 */
- } else if (effective_data_rate == 333 || effective_data_rate ==
400) {
+ } else if (effective_data_rate == 333) {
+ cpo = 0x6; /* READ_LAT + 1 */
+ } else if (effective_data_rate == 400) {
cpo = 0x7; /* READ_LAT + 5/4 */
} else {
/* Automatic calibration */
--
1.5.4
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