On 07/18/2013 01:13 PM, Thierry Reding wrote: > From: Thierry Reding <tred...@nvidia.com> > > Currently all Tegra SoCs are assumed to have 32 byte cache lines. This > isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and > therefore uses a cache line size of 64 bytes. Move the cache line size > setting to the per-SoC common configuration file.
Tom, can these two patches be applied please? _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
