Signed-off-by: Haiying Wang <haiying.w...@freescale.com>
---
drivers/qe/uec.c | 17 +++++++++++++++++
drivers/qe/uec.h | 31 +++++++++++++++++++++++++++++--
2 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index deeb947..7649f9f 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -577,6 +577,10 @@ static int uec_set_mac_if_mode(uec_private_t *uec,
enet_interface_e if_mode)
maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
upsmr |= (UPSMR_R10M | UPSMR_RMM);
break;
+ case ENET_1000_SGMII:
+ maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
+ upsmr |= UPSMR_SGMM;
+ break;
default:
return -EINVAL;
break;
@@ -1276,6 +1280,18 @@ static int uec_startup(uec_private_t *uec)
out_be32(&uec_regs->utbipar, utbipar);
+ /* Configure the TBI for SGMII operation */
+ if (uec->uec_info->enet_interface == ENET_1000_SGMII) {
+ uec_write_phy_reg(uec->dev, uec_regs->utbipar,
+ ENET_TBI_MII_ANA, TBIANA_SETTINGS);
+
+ uec_write_phy_reg(uec->dev, uec_regs->utbipar,
+ ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
+
+ uec_write_phy_reg(uec->dev, uec_regs->utbipar,
+ ENET_TBI_MII_CR, TBICR_SETTINGS);
+ }
+
/* Allocate Tx BDs */
length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
@@ -1565,6 +1581,7 @@ int uec_initialize(int index)
devlist[index] = dev;
uec->uec_info = uec_info;
+ uec->dev = dev;
sprintf(dev->name, "FSL UEC%d", index);
dev->iobase = 0;
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index 411f0d2..5497b06 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Dave Liu <dave...@freescale.com>
* based on source code of Shlomi Gridish
@@ -47,6 +47,7 @@
#define UPSMR_CAM 0x00000400 /* CAM Address Matching */
#define UPSMR_BRO 0x00000200 /* Broadcast Address */
#define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */
+#define UPSMR_SGMM 0x00000020 /* SGMII mode */
#define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1)
@@ -621,6 +622,31 @@ typedef enum enet_tbi_mii_reg {
ENET_TBI_MII_TBICON = 0x11
} enet_tbi_mii_reg_e;
+/* TBI MDIO register bit fields*/
+#define TBICON_CLK_SELECT 0x0020
+#define TBIANA_ASYMMETRIC_PAUSE 0x0100
+#define TBIANA_SYMMETRIC_PAUSE 0x0080
+#define TBIANA_HALF_DUPLEX 0x0040
+#define TBIANA_FULL_DUPLEX 0x0020
+#define TBICR_PHY_RESET 0x8000
+#define TBICR_ANEG_ENABLE 0x1000
+#define TBICR_RESTART_ANEG 0x0200
+#define TBICR_FULL_DUPLEX 0x0100
+#define TBICR_SPEED1_SET 0x0040
+
+#define TBIANA_SETTINGS ( \
+ TBIANA_ASYMMETRIC_PAUSE \
+ | TBIANA_SYMMETRIC_PAUSE \
+ | TBIANA_FULL_DUPLEX \
+ )
+
+#define TBICR_SETTINGS ( \
+ TBICR_PHY_RESET \
+ | TBICR_ANEG_ENABLE \
+ | TBICR_FULL_DUPLEX \
+ | TBICR_SPEED1_SET \
+ )
+
/* UEC number of threads
*/
typedef enum uec_num_of_threads {
@@ -645,7 +671,8 @@ typedef enum enet_interface {
ENET_1000_RGMII_ID,
ENET_1000_RGMII_RXID,
ENET_1000_TBI,
- ENET_1000_RTBI
+ ENET_1000_RTBI,
+ ENET_1000_SGMII
} enet_interface_e;
/* UEC initialization info struct
--
1.6.0.2
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