On Oct 23, 2009, at 3:55 PM, Peter Tyser wrote: > This change has 3 goals: > - Have secondary cores be released into spin loops at their 'true' > address in SDRAM. Previously, secondary cores were put into spin > loops in the 0xfffffxxx address range which required that boot page > translation was always enabled while cores were in their spin loops. > > - Allow the TLB window that the primary core uses to access the > secondary cores boot page to be placed at any address. Previously, a > TLB window at 0xfffff000 was always used to access the seconary > cores' > boot page. This TLB address requirement overlapped with other > peripherals on some boards (eg XPedite5370). By default, the boot > page TLB will still use the 0xfffffxxx address range, but this can be > overridden on a board-by-board basis by defining a custom > CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page > remains in use while U-Boot executes. Previously it was only > temporarily used, then restored to its initial value. > > - Allow Boot Page Translation to be disabled on bootup. Previously, > Boot Page Translation was always left enabled after secondary cores > were brought out of reset. This caused the 0xfffffxxx address range > to somewhat "magically" be translated to an address in SDRAM. Some > boards may not want this oddity in their memory map, so defining > CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after > the secondary cores are initialized. > > These changes are only applicable to 85xx boards with CONFIG_MP > defined. > > Signed-off-by: Peter Tyser <pty...@xes-inc.com> > --- > Hi Kumar, > Hopefully this isn't too invasive... I tried to address your previous > v2 comments of: > - Its possible that the location in memory is not mapped in the TLBs. > We typically max out @ 2G of DDR mapped (via the TLBs). So what > happens if we have 3G of DDR? > - We expect the the address that the spin table is at to be marked > cache-inhibited. > > Changes since v1: > - Use clrbits_be32() instead of in/out_be32() > > - Boot page translation is only disabled when > CONFIG_MPC8xxx_DISABLT_BPTR > is defined. > > - Instead of zeroing out BPTR when disabling translation, this > patch only disables translation, but maintins the translation > address. This should make it easier to properly re-enable > translation if need be. > > Changes since v2: > - Use CONFIG_BPTR_VIRT_ADDR to determine virtual address of secondary > cores' boot page > - Split get_spin_addr() into get_[phys|virt]_addr() > > cpu/mpc85xx/fdt.c | 2 +- > cpu/mpc85xx/mp.c | 70 +++++++++++++++++++++++++++++ > +---------------- > cpu/mpc85xx/mp.h | 3 +- > cpu/mpc85xx/release.S | 34 +++++++++++++++++++--- > include/asm-ppc/config.h | 10 ++++++ > 5 files changed, 88 insertions(+), 31 deletions(-)
applied to 85xx - k _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot