Add common board configuration code which uses serdes
configuration information gotten from common fsl_serdes
APIs to initialize peripheral ports like PCIE, SGMII and
SRIO. Disable unused block when not configured.
Also update device trees to remove unused nodes to
prevent these devices/buses being initialized in kernel.
Signed-off-by: Li Yang <le...@freescale.com>
---
cpu/mpc85xx/Makefile | 1 +
cpu/mpc85xx/cpu_init.c | 14 ++--
cpu/mpc85xx/serdes.c | 217 ++++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/fsl_serdes.h | 50 ++++++++++
4 files changed, 275 insertions(+), 7 deletions(-)
create mode 100644 cpu/mpc85xx/serdes.c
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index 56de7eb..018ebc9 100644
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -62,6 +62,7 @@ COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
COBJS-$(CONFIG_PCI) += pci.o
COBJS-$(CONFIG_QE) += qe_io.o
COBJS-$(CONFIG_CPM2) += serial_scc.o
+COBJS-$(CONFIG_FSL_SERDES) += serdes.o
COBJS = $(COBJS-y)
COBJS += cpu.o
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 0041a60..05133d3 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -33,14 +33,11 @@
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
#include "mp.h"
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_MPC8536
-extern void fsl_serdes_init(void);
-#endif
-
#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -237,9 +234,7 @@ void cpu_init_f (void)
/* Config QE ioports */
config_qe_ioports();
#endif
-#if defined(CONFIG_MPC8536)
- fsl_serdes_init();
-#endif
+
#if defined(CONFIG_FSL_DMA)
dma_init();
#endif
@@ -374,6 +369,11 @@ int cpu_init_r(void)
qe_reset();
#endif
+ /* XXX: remove MPC8536 eventually */
+#if defined(CONFIG_FSL_SERDES) || defined(CONFIG_MPC8536)
+ fsl_serdes_init();
+#endif
+
#if defined(CONFIG_MP)
setup_mp();
#endif
diff --git a/cpu/mpc85xx/serdes.c b/cpu/mpc85xx/serdes.c
new file mode 100644
index 0000000..87ec221
--- /dev/null
+++ b/cpu/mpc85xx/serdes.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_pci.h>
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif
+
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif
+
+#ifdef CONFIG_PCIE3
+static struct pci_controller pcie3_hose;
+#endif
+
+void mpc85xx_serdes_board_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ struct fsl_pci_info pci_info[3];
+ u32 devdisr, host_agent;
+ int first_free_busno = 0;
+ int num = 0;
+ int rio = 0;
+
+ int pcie_ep;
+
+ devdisr = in_be32(&gur->devdisr);
+ host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
+
+ debug(" mpc85xx_serdes_board_init: devdisr=%x, host_agent=%x\n",
+ devdisr, host_agent);
+
+ if (is_serdes_configured(SGMII_TSEC1))
+ puts(" eTSEC1 is in sgmii mode.\n");
+ if (is_serdes_configured(SGMII_TSEC2))
+ puts(" eTSEC2 is in sgmii mode.\n");
+ if (is_serdes_configured(SGMII_TSEC3))
+ puts(" eTSEC3 is in sgmii mode.\n");
+
+ puts("\n");
+#ifdef CONFIG_PCIE1
+ pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
+
+ if (is_serdes_configured(PCIE1) && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
+ set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS,
+ law_size_bits(CONFIG_SYS_PCIE1_MEM_SIZE),
+ LAW_TRGT_IF_PCIE_1);
+ set_next_law(CONFIG_SYS_PCIE1_IO_PHYS,
+ law_size_bits(CONFIG_SYS_PCIE1_IO_SIZE),
+ LAW_TRGT_IF_PCIE_1);
+
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ printf(" PCIE1 used as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
+ } else {
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE);
+ printf(" PCIE1: disabled\n");
+ }
+ puts("\n");
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
+#endif
+
+#ifdef CONFIG_PCIE2
+ pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
+
+ if (is_serdes_configured(PCIE2) && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
+ set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS,
+ law_size_bits(CONFIG_SYS_PCIE2_MEM_SIZE),
+ LAW_TRGT_IF_PCIE_2);
+ set_next_law(CONFIG_SYS_PCIE2_IO_PHYS,
+ law_size_bits(CONFIG_SYS_PCIE2_IO_SIZE),
+ LAW_TRGT_IF_PCIE_2);
+
+ SET_STD_PCIE_INFO(pci_info[num], 2);
+ printf(" PCIE2 used as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie2_hose, first_free_busno);
+
+ } else {
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2);
+ printf(" PCIE2: disabled\n");
+ }
+ puts("\n");
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
+#endif
+
+#ifdef CONFIG_PCIE3
+ pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
+
+ if (is_serdes_configured(PCIE3) && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
+ set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS,
+ law_size_bits(CONFIG_SYS_PCIE3_MEM_SIZE),
+ LAW_TRGT_IF_PCIE_3);
+ set_next_law(CONFIG_SYS_PCIE3_IO_PHYS,
+ law_size_bits(CONFIG_SYS_PCIE3_IO_SIZE),
+ LAW_TRGT_IF_PCIE_3);
+
+ SET_STD_PCIE_INFO(pci_info[num], 3);
+ printf(" PCIE3 used as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie3_hose, first_free_busno);
+ } else {
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3);
+ printf(" PCIE3: disabled\n");
+ }
+ puts("\n");
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
+#endif
+
+#ifdef CONFIG_SRIO
+ if (is_serdes_configured(SRIO1) && !(devdisr & MPC85xx_DEVDISR_SRIO)){
+ set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
+ law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
+ LAW_TRGT_IF_RIO);
+
+ rio = 1;
+ printf(" SRIO1 enabled\n");
+ } else {
+ printf(" SRIO1: disabled\n");
+ }
+
+ if (is_serdes_configured(SRIO2) && !(devdisr & MPC85xx_DEVDISR_SRIO)){
+ set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS,
+ law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE),
+ LAW_TRGT_IF_RIO_2);
+
+ printf(" SRIO2 enabled\n");
+ } else {
+ printf(" SRIO2: disabled\n");
+ if (rio == 0)
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_SRIO);
+
+ }
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_SRIO); /* disable */
+#endif
+}
+
+void ft_mpc85xx_serdes_board_setup(void *blob)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 devdisr = in_be32(&gur->devdisr);
+
+#ifdef CONFIG_PCIE1
+ if (devdisr & MPC85xx_DEVDISR_PCIE)
+ fdt_del_node_by_path(blob, PCIE1_ALIAS_NAME);
+ else
+ ft_fsl_pci_setup(blob, PCIE1_ALIAS_NAME, &pcie1_hose);
+#else
+ fdt_del_node_by_path(blob, PCIE1_ALIAS_NAME);
+#endif
+#ifdef CONFIG_PCIE2
+ if (devdisr & MPC85xx_DEVDISR_PCIE2)
+ fdt_del_node_by_path(blob, PCIE2_ALIAS_NAME);
+ else
+ ft_fsl_pci_setup(blob, PCIE2_ALIAS_NAME, &pcie2_hose);
+#else
+ fdt_del_node_by_path(blob, PCIE2_ALIAS_NAME);
+#endif
+#ifdef CONFIG_PCIE3
+ if (devdisr & MPC85xx_DEVDISR_PCIE3)
+ fdt_del_node_by_path(blob, PCIE3_ALIAS_NAME);
+ else
+ ft_fsl_pci_setup(blob, PCIE3_ALIAS_NAME, &pcie3_hose);
+#else
+ fdt_del_node_by_path(blob, PCIE3_ALIAS_NAME);
+#endif
+#ifdef CONFIG_SRIO
+ if (devdisr & MPC85xx_DEVDISR_SRIO) {
+ fdt_del_node_by_path(blob, SRIO1_ALIAS_NAME);
+ fdt_del_node_by_path(blob, SRIO2_ALIAS_NAME);
+ } else {
+ if (!is_serdes_configured(SRIO1))
+ fdt_del_node_by_path(blob, SRIO1_ALIAS_NAME);
+ if (!is_serdes_configured(SRIO2))
+ fdt_del_node_by_path(blob, SRIO2_ALIAS_NAME);
+ }
+#else
+ fdt_del_node_by_path(blob, SRIO1_ALIAS_NAME);
+ fdt_del_node_by_path(blob, SRIO2_ALIAS_NAME);
+#endif
+}
diff --git a/include/asm-ppc/fsl_serdes.h b/include/asm-ppc/fsl_serdes.h
index 6da4b6f..b75d736 100644
--- a/include/asm-ppc/fsl_serdes.h
+++ b/include/asm-ppc/fsl_serdes.h
@@ -3,6 +3,7 @@
#include <config.h>
+#ifdef CONFIG_MPC83xx
#define FSL_SERDES_CLK_100 (0 << 28)
#define FSL_SERDES_CLK_125 (1 << 28)
#define FSL_SERDES_CLK_150 (3 << 28)
@@ -17,5 +18,54 @@ extern void fsl_setup_serdes(u32 offset, char proto, u32
rfcks, char vdd);
#else
static void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) {}
#endif /* CONFIG_FSL_SERDES */
+#endif /* CONFIG_MPC83xx */
+
+#ifdef CONFIG_MPC85xx
+enum srds_prtcl {
+ NONE = 0,
+ PCIE1,
+ PCIE2,
+ PCIE3,
+ SRIO1,
+ SRIO2,
+ SGMII_TSEC1,
+ SGMII_TSEC2,
+ SGMII_TSEC3,
+};
+
+#if defined(CONFIG_MPC8548)
+#define PCIE1_ALIAS_NAME "pci2"
+#elif defined(CONFIG_MPC8536)
+#define PCIE1_ALIAS_NAME "pci3"
+#define PCIE2_ALIAS_NAME "pci2"
+#define PCIE3_ALIAS_NAME "pci1"
+#else
+#define PCIE1_ALIAS_NAME "pci2"
+#define PCIE2_ALIAS_NAME "pci1"
+#define PCIE3_ALIAS_NAME "pci0"
+#endif
+
+#define SRIO1_ALIAS_NAME "rio0"
+#define SRIO2_ALIAS_NAME "rio1"
+
+extern void mpc85xx_serdes_board_init(void);
+extern void ft_mpc85xx_serdes_board_setup(void *blob);
+
+#ifdef CONFIG_FSL_SERDES
+extern void fsl_serdes_init(void);
+extern int is_serdes_configured(enum srds_prtcl prtcl);
+#else
+
+/* XXX: MPC8536 should eventually use CONFIG_FSL_SERDES */
+#ifndef CONFIG_MPC8536
+void fsl_serdes_init(void) {}
+#endif
+
+int is_serdes_configured(enum srds_prtcl prtcl)
+{
+ return 1;
+}
+#endif /* CONFIG_FSL_SERDES */
+#endif /* CONFIG_MPC85xx */
#endif /* __FSL_SERDES_H */
--
1.6.4
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
