On Wed, Jan 6, 2010 at 12:48 AM, Nishanth Menon
<menon.nisha...@gmail.com> wrote:
> On Tue, Jan 5, 2010 at 10:11 AM, Khasim Syed Mohammed
> <kha...@beagleboard.org> wrote:
>> From 1bb1a2441e6f54f3fe7d71e30da3bc22732aa7d3 Mon Sep 17 00:00:00 2001
>> From: Syed Mohammed Khasim <kha...@ti.com>
>> Date: Tue, 5 Jan 2010 20:28:01 +0530
>> Subject: [PATCH] Configure PRCM registers to support 720 Mhz on Beagle
>> REV C4 and Latest OMAP3530 ES version
> watch the subject length ;)..
>
>>
> no commit message?
>
Will correct these :)
> Why do you need to bump up to 720Mhz in u-boot? can't you do that as
> part of dvfs in kernel? wont that be better? can't you do a standard
> boot or is this device never capable of OPP3?
>
Question is why not in u-boot as well ?? Kernel can do its own stuff
later and this device supports the same.
>> Signed-off-by: Syed Mohammed Khasim <kha...@ti.com>
>> ---
>> board/ti/beagle/beagle.c | 9 +++++++--
>> cpu/arm_cortexa8/omap3/clock.c | 22 ++++++++++++++++++++++
>> drivers/power/twl4030.c | 21 +++++++++++++++++++++
>> 3 files changed, 50 insertions(+), 2 deletions(-)
>>
>> diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
>> index 17840cf..d76df30 100644
>> --- a/board/ti/beagle/beagle.c
>> +++ b/board/ti/beagle/beagle.c
>> @@ -122,9 +122,16 @@ int misc_init_r(void)
>> struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
>> struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
>>
>> + beagle_identify();
>> +
>> twl4030_power_init();
>> twl4030_led_init();
>>
>> + if (beagle_revision == REVISION_C4) {
>> + twl4030_power_init_es3_720();
>> + prcm_config_720mhz();
>> + }
>> +
>> /* Configure GPIOs to output */
>> writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
>> writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
>> @@ -136,8 +143,6 @@ int misc_init_r(void)
>> writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
>> GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
>>
>> - beagle_identify();
>> -
>> dieid_num_r();
>>
>> return 0;
>> diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c
>> index 174c453..ab96a46 100644
>> --- a/cpu/arm_cortexa8/omap3/clock.c
>> +++ b/cpu/arm_cortexa8/omap3/clock.c
>> @@ -402,3 +402,25 @@ void per_clocks_enable(void)
>>
>> sdelay(1000);
>> }
>> +
>> +/*
>> + * Configure PRCM registers to get 720 Mhz
>> + *
>> + * NOTE: N value doesn't change, only M gets affected
>> + */
>> +
> unwanted EOL?
noted, will change.
>> +void prcm_config_720mhz (void)
> you are assuming 3430 ONLY support here, how abt 3630 and family?
Not sure, I don't have a 3630 version of a board, if some one wants to
add support for the same, I am open. For now I will focus on 3430 /
3530 versions.
>
>> +{
>> + struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
>> +
>> + /* Unlock MPU DPLL (slows things down, and needed later) */
>> + sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
>> + wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, LDELAY);
>> +
>> + /* Set M */
>> + sr32(&prcm_base->clksel1_pll_mpu, 8, 11, 0x2D0);
>> +
>> + /* lock mode */
>> + sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
>> + wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, LDELAY);
>> +}
>> diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c
>> index eb066cb..fa1c7d5 100644
>> --- a/drivers/power/twl4030.c
>> +++ b/drivers/power/twl4030.c
>> @@ -68,6 +68,8 @@ void twl4030_power_reset_init(void)
>> #define DEV_GRP_ALL 0xE0
>> #define VPLL2_VSEL_18 0x05
>> #define VDAC_VSEL_18 0x03
>> +#define VAUX2_VSEL_18 0x05
>> +#define VDD1_VSEL_14 0x40
>>
>> void twl4030_power_init(void)
>> {
>> @@ -113,3 +115,22 @@ void twl4030_power_mmc_init(void)
>> twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
>> TWL4030_PM_RECEIVER_VMMC1_DEDICATED);
>> }
>> +
>> +void twl4030_power_init_es3_720(void)
> naming is confusing - is it 4030 or 3530 ES you are trying to describe here?
yeah, looks bit confusing. Will change it to an appropriate one.
>
>> +{
>> + unsigned char byte;
>> +
>> + /* VAUX2 needs to be 1.8v */
>> + byte = DEV_GRP_P1;
>> + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
>> + TWL4030_PM_RECEIVER_VAUX2_DEV_GRP);
>> +
>> + byte = VAUX2_VSEL_18;
>> + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
>> + TWL4030_PM_RECEIVER_VAUX2_DEDICATED);
>> +
>> + /* Put VSEL for VDD1 to 1.4v to get 720Mhz */
>> + byte = VDD1_VSEL_14;
>> + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
>> + TWL4030_PM_RECEIVER_VDD1_VSEL);
>> +}
> huh? you may want to NOT do this, instead introduce a generic voltage
> rail API which is called from silicon/board specific file.
>
Already there are three levels of APIs, I don't mind adding another
one. Will do that.
Thanks a lot for the review. will re-submit this patch.
Regards,
Khasim
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