On Thu, Apr 18, 2024 at 11:14 AM Marek Vasut <ma...@denx.de> wrote: > > On 4/18/24 7:56 PM, Tim Harvey wrote: > > Add support for PCIe clocks required to enable PCIe support on > > iMX8MM SoC. > > > > Signed-off-by: Tim Harvey <thar...@gateworks.com> > > --- > > v2: no changes > > --- > > drivers/clk/imx/clk-imx8mm.c | 21 +++++++++++++++++++++ > > 1 file changed, 21 insertions(+) > > > > diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c > > index b5c253e49663..c2f01b385201 100644 > > --- a/drivers/clk/imx/clk-imx8mm.c > > +++ b/drivers/clk/imx/clk-imx8mm.c > > @@ -66,6 +66,15 @@ static const char *imx8mm_i2c3_sels[] = > > {"clock-osc-24m", "sys_pll1_160m", "sys_ > > static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", > > "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", > > "video_pll1_out", "audio_pll2_out", > > "sys_pll1_133m", }; > > > > +static const char *imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", > > "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m", > > + "sys_pll1_800m", > > "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", }; > > + > > +static const char *imx8mm_pcie1_phy_sels[] = {"clock-osc-24m", > > "sys_pll2_100m", "sys_pll2_500m", "clk_ext1", "clk_ext2", > > + "clk_ext3", "clk_ext4", > > "sys_pll1_400m", }; > > + > > +static const char *imx8mm_pcie1_aux_sels[] = {"clock-osc-24m", > > "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out", > > + "sys_pll2_100m", > > "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", }; > > + > > #ifndef CONFIG_SPL_BUILD > > static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", > > "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", > > "sys_pll3_out", "clk_ext1", > > "sys_pll1_80m", "video_pll1_out", }; > > @@ -256,6 +265,15 @@ static int imx8mm_clk_probe(struct udevice *dev) > > imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + > > 0x8b80)); > > > > /* IP */ > > + clk_dm(IMX8MM_CLK_PCIE1_CTRL, > > + imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels, > > + base + 0xa300)); > > + clk_dm(IMX8MM_CLK_PCIE1_PHY, > > + imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels, > > + base + 0xa380)); > > + clk_dm(IMX8MM_CLK_PCIE1_AUX, > > + imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels, > > + base + 0xa400)); > > Maybe this should be behind IS_ENABLED() like the SPI clock to avoid > growth of SPL ?
Makes sense... I'll add that in a v3. Thanks for the review! Best Regards, Tim