[PATCH RFC 4/9] sunxi: video: support LCD on H6/D1

[John Watts]

The H6/D1/R528 don't require any big changes, just some small
tweaks to support new clock and reset logic.

Signed-off-by: John Watts <cont...@jookia.org>
---
 drivers/video/sunxi/lcdc.c      | 20 ++++++++++++++++++++
 drivers/video/sunxi/sunxi_lcd.c |  6 ++++--
 2 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c
index 73033c3b85..ea21d602be 100644
--- a/drivers/video/sunxi/lcdc.c
+++ b/drivers/video/sunxi/lcdc.c
@@ -277,6 +277,12 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int 
dotclock,
                }
        }
 
+#if IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)
+       /* No need to clock doubling, just ask for a higher PLL clock */
+       best_double = 0;
+       step *= 2;
+#endif
+
 #ifdef CONFIG_MACH_SUN6I
        /*
         * Use the MIPI pll if we've been unable to find any matching setting
@@ -302,6 +308,19 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int 
dotclock,
                      best_double + 1, step, best_n, best_m);
        }
 
+#if IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)
+       if (tcon == 0) {
+               writel(CCM_TCON0_CTRL_VIDEO0_4X | CCM_TCON0_CTRL_ENABLE,
+                      &ccm->tcon_lcd0_clk_cfg);
+               setbits_le32(&ccm->tcon_lcd_gate_reset, BIT(RESET_SHIFT));
+               setbits_le32(&ccm->tcon_lcd_gate_reset, BIT(GATE_SHIFT));
+       } else {
+               writel(CCM_TCON1_CTRL_VIDEO0_4X | CCM_TCON1_CTRL_ENABLE,
+                      &ccm->tcon_tv0_clk_cfg);
+               setbits_le32(&ccm->tcon_tv_gate_reset, BIT(RESET_SHIFT));
+               setbits_le32(&ccm->tcon_tv_gate_reset, BIT(GATE_SHIFT));
+       }
+#else
        if (tcon == 0) {
                u32 pll;
 
@@ -329,6 +348,7 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int 
dotclock,
                        setbits_le32(&ccm->lcd0_ch1_clk_cfg,
                                     CCM_LCD_CH1_CTRL_HALF_SCLK1);
        }
+#endif
 #endif
 
        *clk_div = best_m;
diff --git a/drivers/video/sunxi/sunxi_lcd.c b/drivers/video/sunxi/sunxi_lcd.c
index 7a01cc343c..3b0e63233f 100644
--- a/drivers/video/sunxi/sunxi_lcd.c
+++ b/drivers/video/sunxi/sunxi_lcd.c
@@ -26,7 +26,7 @@ struct sunxi_lcd_priv {
 
 static void sunxi_lcdc_config_pinmux(void)
 {
-#ifdef CONFIG_MACH_SUN50I
+#if IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_SUN50I_GEN_H6) || 
IS_ENABLED(CONFIG_MACH_SUN8I_R528)
        int pin;
 
        for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(21); pin++) {
@@ -47,10 +47,12 @@ static int sunxi_lcd_enable(struct udevice *dev, int bpp,
        struct udevice *backlight;
        int clk_div, clk_double, ret;
 
+#if !IS_ENABLED(CONFIG_SUN50I_GEN_H6) && !IS_ENABLED(CONFIG_MACH_SUN8I_R528)
        /* Reset off */
        setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
        /* Clock on */
        setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
+#endif
 
        lcdc_init(lcdc);
        sunxi_lcdc_config_pinmux();
@@ -146,7 +148,7 @@ U_BOOT_DRIVER(sunxi_lcd) = {
        .priv_auto      = sizeof(struct sunxi_lcd_priv),
 };
 
-#ifdef CONFIG_MACH_SUN50I
+#if IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_SUN50I_GEN_H6) || 
IS_ENABLED(CONFIG_MACH_SUN8I_R528)
 U_BOOT_DRVINFO(sunxi_lcd) = {
        .name = "sunxi_lcd"
 };

-- 
2.44.0