Hi Aneesh, On Thu, Jan 19, 2012 at 11:17 AM, Aneesh V <ane...@ti.com> wrote: > On Thursday 19 January 2012 12:23 PM, Sughosh Ganu wrote: >> Tried a few things on my end. >> * Read the D-cache value in the spl, and confirmed that the data >> cache is indeed not enabled. > What is the value of the B bit in CP15 SCR register? I wonder if RBL is > doing all the IMB operations required after copying the SPL image and > before executing it. IMB is required for consistency between data and > instruction sides.
Only if caches are used, right? Or also without caches? Tom wrote that RBL does not turn on cache. Regards, Christian _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
