> On May 18, 2026, at 21:55, ron minnich <[email protected]> wrote:
>
> There's a reason I started the RISC-V port, a year ago.
>
> background: I wrote the first SBI after the berkeley one, in 2014. I
> put a lot of work into making it small, in every sense: space, time,
> complexity.
>
> The current standard, OpenSBI, is big in every sense: space, time, complexity.
>
> So I intend to show an alternate path, starting with this port.
And I think it’s exciting, and the right direction to take. But it does depend
on the silicon vendors providing the kinds of chips that we want, or else for
us to eventually be able to make them the way we want. Being able to do that
would also enable experiments with things like type-tagged memory, persistent
memory, higher-density clusters/grids, etc.
In the meantime, I just hope the desire of the new-on-the-block vendors to
reduce cost and thumb their noses at the incumbents will provide enough
motivation to leave unnecessary crap off the chips.
Fully-open design would be the next level: open-source layout, peripherals and
GPU without IP restrictions.
But I’m new to writing code for it, so it will take me time to come up to speed
with what we have, and that’s another reason I got interested: maybe it’s an
architecture worth learning, being the first of its kind, and designed by
people who thought it through and tried to come up with an ideal architecture
rather than being constrained by backwards compatibility and tradition. Just
like Plan 9 was created by rethinking OS design. And they could both end up
“winning” (being used more widely at least) just by being faster, lighter,
cheaper, suitable for “permacomputing” (whatever that turns out to mean).
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