> > The MMU does not support page based virtual memory. I suspect that is a > problem for plan9, unless there is a nommu option.
As someone suggested, Inferno's fine with that, or at least tolerates it. What does the MMU do? On Mon, 14 Sept 2026 at 23:55, Joshua D. Boyd via 9fans <[email protected]> wrote: > > > On September 14, 2026 4:03:48 PM EDT, Shawn Rutledge <[email protected]> > wrote: > >That looks like rather little memory (768k SRAM; 32MB “PSRAM” has some > sort of catch - is it serial-attached and slow?) You’d have a chance with > Inferno though: similar to David Boddie’s microcontroller ports > https://github.com/dboddie/inferno-os (look at branches) except riscv > instead of arm. I haven’t heard of a port to ESP-riscv chips being done > yet. If the LoRa devices with nice screens and keyboards (like LilyGo > T-Deck series) would start using the Risc-V ESP chips, I might be somewhat > interested in that too. But I’m busy enough with the Plan 9 port for now, > which is for Spacemit K1 and K3 so far (much more memory and performance). > > The PSRAM is serial attached. It should have its own MSPI bus for that, > and should be good for a bit less than 200MB/s in bandwidth. > > The PSRAM does get mapped into memory space directly, and it does get > cached. > > The MMU does not support page based virtual memory. I suspect that is a > problem for plan9, unless there is a nommu option. ------------------------------------------ 9fans: 9fans Permalink: https://9fans.topicbox.com/groups/9fans/T925b60c1e0142973-M7e45e7f57d3e679eb64f5690 Delivery options: https://9fans.topicbox.com/groups/9fans/subscription
