http://bugzilla.kernel.org/show_bug.cgi?id=9475
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------- Comment #12 from [EMAIL PROTECTED] 2007-12-06 20:32 -------
Some Intel TSC facts, for the record:
if (family == 6 && model < 14) || (family == 15 && model < 3)
TSC rate = Core MHz rate (ie. it changes with core/bus ratio shifts)
WRMSR on the TSC writes bottom 32-bits, clears upper 32 bits.
For these families with models later than above
TSC rate = constant (does not change with core/bus ratio shifts)
WRMSR TSC writes all 64 bits.
The system here is a family 6, model 13, so it it will
indeed see variable speed.
But note that the bigger problem may be that on all Intel processors
with C3 that have shipped to date, the TSC COMPLETELY STOPS
for the duration of C3.
I believe that tsc_unstable is set upon either of these situations.
I don't follow all the twisty turny paths in the code here --
and it is wonderful that you bisected and found the cause;
but it isn't immediately obvious that this is due to variable
speed TSC, but it may be due to TSC stoppage.
if you disable cpufreq and it goes away, you know it was variable TSC.
if you boot with "idle=poll" and keep cpufreq enabled and it goes
away, then you know it was TSC stoppage.
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