Hi all, I am porting adeos-1.0 to a MIPS processor. The most straight forward activities are porting the inline assembly code for eg enabling/disabling interrupt, save/restoring registers etc.
However, porting the interrupt pipe (and domain switching) is not that trivial since it requires rewriting of the ipipe. MIPS interrupt mechanisms are different then the x86 interrupt handling. Before I start rewriting the interrupt (and exception) pipe mechanism to MIPS architecture, I would like to ask the ADEOS originators what they expect to be reused when doing an architecture port: eg is it just reusing the API or do you also want to reuse the sources (and which ones). I have added some visio drawings with respect to the MIPS interrupt/exception handling to indicate how this takes place on a MIPS. (See attached file: viper_irq_pipeline.vsd)(See attached file: viper_irq.vsd) thank you for the information and kind regards, Toon
viper_irq_pipeline.vsd
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viper_irq.vsd
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