Logan,

I have a super-duper computer proposal that addresses your concerns.
Boiling a large proposal down to a short paragraph, These would be LARGE
sized chips, arranged on a wafer so that they are interconnected
until/unless cut apart. The I/O pin logic on each chip would be large
geometry because it would have to survive, but the remainder would be lots
of redundant pieces, and a "relocatable loader" to load microcode as needed
while dodging new and old defects.

Many of the most obvious challenges evaporate if/when you move to a really
high-level language like APL, which obviously needs a new front-end for
general acceptance, but which is now the ONLY language with semantics
adequate to support extremely large scale integration. With a relocatable
loader to dodge defects at "run time" and "crash time", it makes SO many
other things possible/easy.

During fabrication, the chips would be tested to make sure that they aren't
SO bad that they would have to be discarded, and if not, groups of them, or
even all of them, would be left connected together to form a large
closely-connected network, e.g. with the ability to hand off memory banks
full of information to each other, etc.

With an on-chip task-oriented OS, crashed sub-tasks would simply be rerun
on other hardware while the failing hardware is diagnosed and reconfigured.
Note that asynchronous logic and interconnections provide natural fault
detection, because instead of producing wrong answers, they just stop, so a
watchdog timer is all that is needed for failure detection. Hence, no
matter what went wrong, the worst that would happen would be a short delay
in operation while the system reconfigures and redoes the failed task.

It looks like so long as no more than ~1/10^4 transistors are dead, these
processors will work GREAT. Note that this is close to present yields with
gallium arsenide, which would provide a substantial boost in speed.

Of course this would cost a LOT of money to develop - more than anyone is
now willing to commit to any new product. So, like SO many things here on
the AGI forum, this will sit around until the world changes to a form that
is more ready for such things.

Continuing...
On Thu, Oct 18, 2012 at 5:00 PM, Logan Streondj <[email protected]> wrote:

>
> Steve yes that's the thing, a lot of it has to do with circuit size.
> 40 years ago the circuits used to be much larger and more durable.
>

Even back then, many power transistors were really lots of tiny transistors
connected in parallel, and which would keep running even if a few of them
failed. Many people have used this early form of fault tolerant logic
without even realizing it.

But now with nano-circuits they are extremely tiny, and prone to
> degradation from even the quantum heat-radiation of being at room
> temperature.
>

Yes, any realistic new architecture MUST be able to handle run-time
component failures. Asynchronous logic to detect failures, relocatable
loaders to avoid faults, and a task-oriented on-chip OS to avoid being hurt
by run-time failures seems to be the key to such things.

>
> To make longevity hardware, we really will have to make larger circuit
> sizes, and likely build in some redundancy, like multiple processors.
>

No, you need extreme fault tolerance. The easiest way to achieve this is
with an array processor structure, but with either lots of spare nodes, or
with variable size hardware array rows.

Something like those toffoli gates may allow for 3 dimensional computing,
> so what we lose from circuit density, we can gain by having multiple
> relatively cool layers.
>

IMHO the biggest power-related problem is that "modern" computers handle
the data WAY too many times. A MUCH more efficient approach is "data
chaining", where ALUs are dynamically arranged in a way where a complete
loop iteration is done in a single clock cycle. This eliminates ALL of the
memory references internal to the loops, and is an order of magnitude or so
faster than array processor architectures.

So, until the world becomes ready for such things, I will continue to work
on MUCH less exciting projects.

Steve
=========

> On Thu, Oct 18, 2012 at 12:25 PM, Steve Richfield <
> [email protected]> wrote:
>
>> Logan,
>>
>> On Wed, Oct 17, 2012 at 11:16 PM, Logan Streondj <[email protected]>wrote:
>>
>>> One issue that many seem to overlook, is the longevity of hardware
>>> issue.
>>> Fact is, that most hardware produced today, has a half-life of 4-7
>>> years.
>>>
>>
>> That is because they now use cheap plastic packaging, aluminum bonding
>> wires, and don't gold plate much of anything. The military stuff lasts for
>> about a century.
>>
>> I just purchased a 40-year-old analog computer. It had a broken resistor
>> from shipment because the mounting bolts for a small power transformer had
>> been omitted (possibly from the original factory) so the transformer had
>> bashed the resistor, and it needed some alignment to compensate for its
>> aging components - but the alignment controls were there to align, so this
>> wasn't technically even a "repair". Now, it all checks out and is ready to
>> be put back into service, in this case, to evaluate real-time algorithms
>> for smart hearing aids. With this, prospective algorithms can be programmed
>> in a few minutes, and changes can be made in a minute or so.
>>
>> In this next-generation design, the output is added to what the user
>> hears without it, so the analysis must be instantaneous (a few microseconds
>> of delay are OK, but a millisecond would be disastrous) in order to
>> maintain proper phase relationships. Sure this could conceivably be done
>> digitally, but this would be a big hassle, and there would be no apparent
>> advantage in doing so.
>>
>> Of course I didn't have to go WAY back 40 years to find a suitable
>> computer, but in addition to being quite functional it is a beautiful
>> antique, complete with its glowing Nixie tube digital display. Besides, I
>> only had to pay $312 for it.
>>
>> Steve
>>
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