From: Rex Zhu <rex....@amd.com>

Signed-off-by: Rex Zhu <rex....@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c            |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h            | 28 +++-------------------
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c             |  2 +-
 drivers/gpu/drm/amd/amdgpu/ci_dpm.c                |  2 +-
 drivers/gpu/drm/amd/amdgpu/kv_dpm.c                |  2 +-
 drivers/gpu/drm/amd/amdgpu/si_dpm.c                |  2 +-
 drivers/gpu/drm/amd/include/amd_shared.h           | 23 ++++++++++++++++++
 .../amd/powerplay/hwmgr/process_pptables_v1_0.c    |  4 ++--
 .../gpu/drm/amd/powerplay/hwmgr/processpptables.c  |  2 +-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          | 16 ++-----------
 drivers/gpu/drm/amd/powerplay/inc/power_state.h    |  9 -------
 11 files changed, 36 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
index 14f57d9..4f8d3a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
@@ -554,7 +554,7 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device 
*adev)
                                        ((u8 *)entry + 
sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record));
                        }
                        for (i = 0; i < states->numEntries; i++) {
-                               if (i >= AMDGPU_MAX_VCE_LEVELS)
+                               if (i >= AMD_MAX_VCE_LEVELS)
                                        break;
                                vce_clk = (VCEClockInfo *)
                                        ((u8 *)&array->entries[0] +
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index d06496d..68dac0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -52,17 +52,6 @@ enum amdgpu_dpm_event_src {
        AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
 };
 
-#define AMDGPU_MAX_VCE_LEVELS 6
-
-enum amdgpu_vce_level {
-       AMDGPU_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
-       AMDGPU_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
-       AMDGPU_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
-       AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res 
> 720 */
-       AMDGPU_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 
720 */
-       AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= 
res > 720 */
-};
-
 struct amdgpu_ps {
        u32 caps; /* vbios flags */
        u32 class; /* vbios flags */
@@ -74,7 +63,7 @@ struct amdgpu_ps {
        u32 evclk;
        u32 ecclk;
        bool vce_active;
-       enum amdgpu_vce_level vce_level;
+       enum amd_vce_level vce_level;
        /* asic priv */
        void *ps_priv;
 };
@@ -257,17 +246,6 @@ enum amdgpu_dpm_forced_level {
        AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
 };
 
-struct amdgpu_vce_state {
-       /* vce clocks */
-       u32 evclk;
-       u32 ecclk;
-       /* gpu clocks */
-       u32 sclk;
-       u32 mclk;
-       u8 clk_idx;
-       u8 pstate;
-};
-
 struct amdgpu_dpm_funcs {
        int (*get_temperature)(struct amdgpu_device *adev);
        int (*pre_set_power_state)(struct amdgpu_device *adev);
@@ -409,8 +387,8 @@ struct amdgpu_dpm {
        /* default uvd power state */
        struct amdgpu_ps        *uvd_ps;
        /* vce requirements */
-       struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
-       enum amdgpu_vce_level vce_level;
+       struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
+       enum amd_vce_level vce_level;
        enum amd_pm_state_type state;
        enum amd_pm_state_type user_state;
        u32                     platform_caps;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index accc908..4656ad6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1135,7 +1135,7 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, 
bool enable)
                        mutex_lock(&adev->pm.mutex);
                        adev->pm.dpm.vce_active = true;
                        /* XXX select vce level based on ring/task */
-                       adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL;
+                       adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
                        mutex_unlock(&adev->pm.mutex);
                } else {
                        mutex_lock(&adev->pm.mutex);
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 1d8c375..dc3196e 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -5689,7 +5689,7 @@ static int ci_parse_power_table(struct amdgpu_device 
*adev)
        adev->pm.dpm.num_ps = state_array->ucNumEntries;
 
        /* fill in the vce power states */
-       for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
+       for (i = 0; i < AMD_MAX_VCE_LEVELS; i++) {
                u32 sclk, mclk;
                clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
                clock_info = (union pplib_clock_info *)
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index f8618a3..a03690a 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -2796,7 +2796,7 @@ static int kv_parse_power_table(struct amdgpu_device 
*adev)
        adev->pm.dpm.num_ps = state_array->ucNumEntries;
 
        /* fill in the vce power states */
-       for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
+       for (i = 0; i < AMD_MAX_VCE_LEVELS; i++) {
                u32 sclk;
                clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
                clock_info = (union pplib_clock_info *)
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 8bd0892..1a909fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -7314,7 +7314,7 @@ static int si_parse_power_table(struct amdgpu_device 
*adev)
        adev->pm.dpm.num_ps = state_array->ucNumEntries;
 
        /* fill in the vce power states */
-       for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
+       for (i = 0; i < AMD_MAX_VCE_LEVELS; i++) {
                u32 sclk, mclk;
                clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
                clock_info = (union pplib_clock_info *)
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h 
b/drivers/gpu/drm/amd/include/amd_shared.h
index c934b78c..94ebc32 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -84,6 +84,29 @@ enum amd_powergating_state {
        AMD_PG_STATE_UNGATE,
 };
 
+struct amd_vce_state {
+       /* vce clocks */
+       u32 evclk;
+       u32 ecclk;
+       /* gpu clocks */
+       u32 sclk;
+       u32 mclk;
+       u8 clk_idx;
+       u8 pstate;
+};
+
+
+#define AMD_MAX_VCE_LEVELS 6
+
+enum amd_vce_level {
+       AMD_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
+       AMD_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
+       AMD_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
+       AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 
720 */
+       AMD_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 
*/
+       AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res 
> 720 */
+};
+
 /* CG flags */
 #define AMD_CG_SUPPORT_GFX_MGCG                        (1 << 0)
 #define AMD_CG_SUPPORT_GFX_MGLS                        (1 << 1)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
index 155cd0d..baf0f3d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
@@ -1211,7 +1211,7 @@ static int 
ppt_get_num_of_vce_state_table_entries_v1_0(struct pp_hwmgr *hwmgr)
 }
 
 static int ppt_get_vce_state_table_entry_v1_0(struct pp_hwmgr *hwmgr, uint32_t 
i,
-               struct pp_vce_state *vce_state, void **clock_info, uint32_t 
*flag)
+               struct amd_vce_state *vce_state, void **clock_info, uint32_t 
*flag)
 {
        const ATOM_Tonga_VCE_State_Record *vce_state_record;
        ATOM_Tonga_SCLK_Dependency_Record *sclk_dep_record;
@@ -1315,7 +1315,7 @@ int get_powerplay_table_entry_v1_0(struct pp_hwmgr *hwmgr,
 
        hwmgr->num_vce_state_tables = i = 
ppt_get_num_of_vce_state_table_entries_v1_0(hwmgr);
 
-       if ((i != 0) && (i <= PP_MAX_VCE_LEVELS)) {
+       if ((i != 0) && (i <= AMD_MAX_VCE_LEVELS)) {
                for (j = 0; j < i; j++)
                        ppt_get_vce_state_table_entry_v1_0(hwmgr, j, 
&(hwmgr->vce_states[j]), NULL, &flags);
        }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
index bd1f190..a4e9cf4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
@@ -1523,7 +1523,7 @@ static int get_number_of_vce_state_table_entries(
 
 static int get_vce_state_table_entry(struct pp_hwmgr *hwmgr,
                                                        unsigned long i,
-                                                       struct pp_vce_state 
*vce_state,
+                                                       struct amd_vce_state 
*vce_state,
                                                        void **clock_info,
                                                        unsigned long *flag)
 {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 4f0fedd..e38b999 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -367,7 +367,7 @@ struct pp_table_func {
        int (*pptable_get_vce_state_table_entry)(
                                                struct pp_hwmgr *hwmgr,
                                                unsigned long i,
-                                               struct pp_vce_state *vce_state,
+                                               struct amd_vce_state *vce_state,
                                                void **clock_info,
                                                unsigned long *flag);
 };
@@ -586,18 +586,6 @@ struct phm_microcode_version_info {
        uint32_t NB;
 };
 
-#define PP_MAX_VCE_LEVELS 6
-
-enum PP_VCE_LEVEL {
-       PP_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
-       PP_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
-       PP_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
-       PP_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 
720 */
-       PP_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
-       PP_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res 
> 720 */
-};
-
-
 enum PP_TABLE_VERSION {
        PP_TABLE_V0 = 0,
        PP_TABLE_V1,
@@ -620,7 +608,7 @@ struct pp_hwmgr {
        void *hardcode_pp_table;
        bool need_pp_table_upload;
 
-       struct pp_vce_state vce_states[PP_MAX_VCE_LEVELS];
+       struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
        uint32_t num_vce_state_tables;
 
        enum amd_dpm_forced_level dpm_level;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/power_state.h 
b/drivers/gpu/drm/amd/powerplay/inc/power_state.h
index 9ceaed9..827860f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/power_state.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/power_state.h
@@ -156,15 +156,6 @@ struct pp_power_state {
        struct pp_hw_power_state  hardware;
 };
 
-
-/*Structure to hold a VCE state entry*/
-struct pp_vce_state {
-       uint32_t evclk;
-       uint32_t ecclk;
-       uint32_t sclk;
-       uint32_t mclk;
-};
-
 enum PP_MMProfilingState {
        PP_MMProfilingState_NA = 0,
        PP_MMProfilingState_Started,
-- 
2.5.5

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