On 2017年06月01日 13:29, Huang Rui wrote:
On Thu, Jun 01, 2017 at 12:19:19PM +0800, zhoucm1 wrote:
On 2017年06月01日 00:14, Huang Rui wrote:
Signed-off-by: Huang Rui <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 33 +++++++++++++++++++-------------
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 33 +++++++++++++++++++-------------
2 files changed, 40 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 7c430c4..8cf30b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -31,6 +31,24 @@
#include "soc15_common.h"
+static void gfxhub_v1_0_init_pt_regs(struct amdgpu_device *adev)
+{
+ uint64_t value;
+
+ BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
+ value = adev->gart.table_addr - adev->mc.vram_start
+ + adev->vm_manager.vram_base_offset;
+ value &= 0x0000FFFFFFFFF000ULL;
+ value |= 0x1; /*valid bit*/
+
+ WREG32(SOC15_REG_OFFSET(GC, 0,
+ mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
+ (u32)value);
+ WREG32(SOC15_REG_OFFSET(GC, 0,
+ mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
+ (u32)(value >> 32));
+}
+
int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
{
u32 tmp;
@@ -38,6 +56,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
u32 i;
/* Program MC. */
+ gfxhub_v1_0_init_pt_regs(adev);
+
abstraction is fine, but why you change code location?
Because we would better to align the programming sequence with windows
part.
If you make sure it aligns with windows, then that's good. Otherwise we
should keep same with previous.
Regards,
David Zhou
That's helpful to debug in future.
Thanks,
Ray
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