On Thu, Jul 31, 2025 at 5:58 AM Timur Kristóf <timur.kris...@gmail.com> wrote:
>
> Adjust the nominal (and performance) clocks for DCE 8-10,
> and set them to 625 MHz, which is the value used by the legacy
> display code in amdgpu_atombios_get_clock_info.
>
> This was tested with Hawaii, Tonga and Fiji.
> These GPUs can output 4K 60Hz (10-bit depth) at 625 MHz.
>
> The extra 15% clock was added as a workaround for a Polaris issue
> which uses DCE 11, and should not have been used on DCE 8-10 which
> are already hardcoded to the highest possible display clock.
> Unfortunately, the extra 15% was mistakenly copied and kept
> even on code paths which don't affect Polaris.
>
> This commit fixes that and also adds a check to make sure
> not to exceed the maximum DCE 8-10 display clock.
>
> Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for Polaris")
> Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
> Signed-off-by: Timur Kristóf <timur.kris...@gmail.com>
>
> x
Stray x here. with that fixed:
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> .../drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 12 +++++-------
> 1 file changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> index 26feefbb8990..69e9540f553b 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> @@ -72,9 +72,9 @@ static const struct state_dependent_clocks
> dce80_max_clks_by_state[] = {
> /* ClocksStateLow */
> { .display_clk_khz = 352000, .pixel_clk_khz = 330000},
> /* ClocksStateNominal */
> -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
> +{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 },
> /* ClocksStatePerformance */
> -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
> +{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 } };
>
> int dentist_get_divider_from_did(int did)
> {
> @@ -400,11 +400,9 @@ static void dce_update_clocks(struct clk_mgr
> *clk_mgr_base,
> {
> struct clk_mgr_internal *clk_mgr_dce =
> TO_CLK_MGR_INTERNAL(clk_mgr_base);
> struct dm_pp_power_level_change_request level_change_req;
> - int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
> -
> - /*TODO: W/A for dal3 linux, investigate why this works */
> - if (!clk_mgr_dce->dfs_bypass_active)
> - patched_disp_clk = patched_disp_clk * 115 / 100;
> + const int max_disp_clk =
> +
> clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
> + int patched_disp_clk = MIN(max_disp_clk,
> context->bw_ctx.bw.dce.dispclk_khz);
>
> level_change_req.power_level =
> dce_get_required_clocks_state(clk_mgr_base, context);
> /* get max clock state from PPLIB */
> --
> 2.50.1
>
