On 16-Dec-25 10:25 PM, Alex Deucher wrote:
On Wed, Dec 3, 2025 at 8:05 AM Lijo Lazar <[email protected]> wrote:
Add an ioctl to return size information required for CWSR regions.
Signed-off-by: Lijo Lazar <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 21 +++++++++++++++++++++
include/uapi/drm/amdgpu_drm.h | 16 ++++++++++++++++
2 files changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 398d6c8d343c..848405c37bd5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -1368,6 +1368,27 @@ int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file *filp)
return -EINVAL;
}
}
+ case AMDGPU_INFO_CWSR: {
+ struct drm_amdgpu_info_cwsr cwsr_info;
+ int num_xcc, r;
+
+ fpriv = (struct amdgpu_fpriv *)filp->driver_priv;
+ if (!amdgpu_cwsr_is_enabled(adev) || !fpriv->cwsr_trap)
+ return -EOPNOTSUPP;
+ num_xcc = amdgpu_xcp_get_num_xcc(adev->xcp_mgr, fpriv->xcp_id);
+ cwsr_info.ctl_stack_size =
+ adev->cwsr_info->xcc_ctl_stack_sz * num_xcc;
+ cwsr_info.dbg_mem_size =
+ adev->cwsr_info->xcc_dbg_mem_sz * num_xcc;
+ cwsr_info.min_save_area_size =
+ adev->cwsr_info->xcc_cwsr_sz * num_xcc;
+ r = copy_to_user(out, &cwsr_info,
+ min((size_t)size, sizeof(cwsr_info))) ?
+ -EFAULT :
+ 0;
+ return r;
+ }
+
default:
DRM_DEBUG_KMS("Invalid request %d\n", info->query);
return -EINVAL;
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index c1336ed4ff75..2bb9daafb560 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -1273,6 +1273,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
#define AMDGPU_INFO_GPUVM_FAULT 0x23
/* query FW object size and alignment */
#define AMDGPU_INFO_UQ_FW_AREAS 0x24
+/* query CWSR size and alignment */
+#define AMDGPU_INFO_CWSR 0x25
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
@@ -1636,6 +1638,20 @@ struct drm_amdgpu_info_uq_metadata {
};
};
+/**
+ * struct drm_amdgpu_info_cwsr - cwsr information
+ *
+ * Gives cwsr related size details. User needs to allocate buffer based on
this.
+ */
+struct drm_amdgpu_info_cwsr {
+ /* Control stack size */
+ __u32 ctl_stack_size;
+ /* Debug memory area size */
+ __u32 dbg_mem_size;
How should this be used by the application? Should it be folded into
the save area or ctl stack, or is it just for future use?
This needs to be accounted into the minimum save area size that should
be allocated by application.
amdgpu_cwsr_size_needed() =
return num_xcc *
(adev->cwsr_info->xcc_cwsr_sz + adev->cwsr_info->xcc_dbg_mem_sz);
xcc_cwsr_size = control stack size + workgroup context size.
This interface provides information about the individual size requirements.
Presently, all of these are also calculated by rocr separately -
https://github.com/ROCm/rocm-systems/blob/develop/projects/rocr-runtime/libhsakmt/src/queues.c#L342
Ideally, we prefer rocr to get this information from driver.
Thanks,
Lijo
+ /* Minimu save area size required */
Minimum
Alex
+ __u32 min_save_area_size;
+};
+
/*
* Supported GPU families
*/
--
2.49.0
