From: Dmytro Laktyushkin <[email protected]> Move it out of smu present block for cases where it isn't
Reviewed-by: Ivan Lipski <[email protected]> Signed-off-by: Dmytro Laktyushkin <[email protected]> Signed-off-by: Roman Li <[email protected]> Signed-off-by: Chuanyu Tseng <[email protected]> --- .../gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c index df904b6fafe9..a0296d5f0102 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c @@ -1138,11 +1138,6 @@ void dcn42_clk_mgr_construct( dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 1; clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base); clk_mgr->base.base.clks.ref_dtbclk_khz = dcn42_smu_get_dtbclk(&clk_mgr->base); - - clk_mgr->base.base.bw_params = &dcn42_bw_params; - - if (clk_mgr->base.smu_present) - dcn42_get_smu_clocks(&clk_mgr->base); } /* in case we don't get a value from the BIOS, use default */ if (clk_mgr->base.base.dentist_vco_freq_khz == 0) @@ -1155,6 +1150,10 @@ void dcn42_clk_mgr_construct( /*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/ dcn42_read_ss_info_from_lut(&clk_mgr->base); + + clk_mgr->base.base.bw_params = &dcn42_bw_params; + if (clk_mgr->base.smu_present) + dcn42_get_smu_clocks(&clk_mgr->base); } void dcn42_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int) -- 2.43.0
