From: Roman Li <[email protected]>
[Why]
The DCN42 underflow detection functions in dcn42_optc.c use
OPTC_RSMU_UNDERFLOW register but the register offset definitions
were missing from dcn_4_2_0_offset.h and dcn42_resource.h.
[How]
Add missing register definitions.
Fixes: 66715fc0ecfd ("drm/amd/display: Sync dcn42 with DC 3.2.373")
Reviewed-by: Alex Hung <[email protected]>
Signed-off-by: Roman Li <[email protected]>
Signed-off-by: Chuanyu Tseng <[email protected]>
---
.../gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h | 2 ++
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h | 6 ++++++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
index a9b26df14520..8e7a09402de5 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
@@ -481,6 +481,8 @@
SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),
\
SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst),
\
SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),
\
+ SRI_ARR(OPTC_RSMU_UNDERFLOW, ODM, inst),
\
+ SRI_ARR(OPTC_UNDERFLOW_THRESHOLD, ODM, inst),
\
SRI_ARR(CONTROL, VTG, inst), \
SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \
SRI_ARR(OTG_GSL_CONTROL, OTG, inst), \
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h
index 52fbf2dc1899..3755a984681a 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h
@@ -9036,6 +9036,8 @@
// base address: 0x40
#define regODM1_OPTC_INPUT_GLOBAL_CONTROL
0x1ada
#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX
2
+#define regODM1_OPTC_RSMU_UNDERFLOW
0x1adb
+#define regODM1_OPTC_RSMU_UNDERFLOW_BASE_IDX
2
#define regODM1_OPTC_UNDERFLOW_THRESHOLD
0x1adc
#define regODM1_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX
2
#define regODM1_OPTC_DATA_SOURCE_SELECT
0x1add
@@ -9060,6 +9062,8 @@
// base address: 0x80
#define regODM2_OPTC_INPUT_GLOBAL_CONTROL
0x1aea
#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX
2
+#define regODM2_OPTC_RSMU_UNDERFLOW
0x1aeb
+#define regODM2_OPTC_RSMU_UNDERFLOW_BASE_IDX
2
#define regODM2_OPTC_UNDERFLOW_THRESHOLD
0x1aec
#define regODM2_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX
2
#define regODM2_OPTC_DATA_SOURCE_SELECT
0x1aed
@@ -9084,6 +9088,8 @@
// base address: 0xc0
#define regODM3_OPTC_INPUT_GLOBAL_CONTROL
0x1afa
#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX
2
+#define regODM3_OPTC_RSMU_UNDERFLOW
0x1afb
+#define regODM3_OPTC_RSMU_UNDERFLOW_BASE_IDX
2
#define regODM3_OPTC_UNDERFLOW_THRESHOLD
0x1afc
#define regODM3_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX
2
#define regODM3_OPTC_DATA_SOURCE_SELECT
0x1afd
--
2.43.0
