From: Roman Li <[email protected]> [Why] The invalid register field access causes ASSERT(mask != 0) to fire in set_reg_field_values() during display enable.
WARNING: at drivers/gpu/drm/amd/amdgpu/../display/dc/dc_helper.c:100 set_reg_field_values.isra.0+0xcf/0xf0 [amdgpu] Call Trace: <TASK> generic_reg_update_ex+0x66/0x1d0 [amdgpu] dccg401_set_dpstreamclk+0xed/0x350 [amdgpu] dcn401_enable_stream+0x165/0x370 [amdgpu] link_set_dpms_on+0x6e9/0xe90 [amdgpu] dce110_apply_single_controller_ctx_to_hw+0x343/0x530 [amdgpu] dce110_apply_ctx_to_hw+0x1f6/0x2d0 [amdgpu] dc_commit_state_no_check+0x49a/0xe20 [amdgpu] dc_commit_streams+0x354/0x570 [amdgpu] amdgpu_dm_atomic_commit_tail+0x6f8/0x3fc0 [amdgpu] DCN4.x hardware does not have DPSTREAMCLK_GATE_DISABLE and DPSTREAMCLK_ROOT_GATE_DISABLE fields in DCCG_GATE_DISABLE_CNTL3. These global fields only exist in DCN3.1.x hardware. [How] Remove the call that tries to update non-existent fields in CNTL3. DCN4.x uses per-instance fields in CNTL5 instead, which are already correctly programmed in the switch cases above. Reviewed-by: Dillon Varone <[email protected]> Signed-off-by: Roman Li <[email protected]> Signed-off-by: Chuanyu Tseng <[email protected]> --- drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c index 0cdf93c614b7..f4ead86c9a96 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c @@ -526,10 +526,6 @@ static void dccg401_enable_dpstreamclk(struct dccg *dccg, int otg_inst, int dp_h BREAK_TO_DEBUGGER(); return; } - if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) - REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, - DPSTREAMCLK_GATE_DISABLE, 1, - DPSTREAMCLK_ROOT_GATE_DISABLE, 1); } void dccg401_disable_dpstreamclk(struct dccg *dccg, int dp_hpo_inst) -- 2.43.0
