From: Rafal Ostrowski <[email protected]> [Why] FPU guards (DC_FP_START/DC_FP_END) are required to wrap around code that can manipulates floats. To do this properly, the FPU guards must be used in a file that is not compiled as a FPU unit. If the guards are used in a file that is a FPU unit, other sections in the file that aren't guarded may be end up being compiled to use FPU operations.
[How] Added DC_FP_START and DC_FP_END to DC functions that call DML functions using FPU. Reviewed-by: Dillon Varone <[email protected]> Signed-off-by: Rafal Ostrowski <[email protected]> Signed-off-by: Alex Hung <[email protected]> --- .../gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 25 ++++++- .../gpu/drm/amd/display/amdgpu_dm/dc_fpu.h | 17 ++++- .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 2 - .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 - drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +- .../gpu/drm/amd/display/dc/core/dc_state.c | 75 ++++++++++++++----- .../gpu/drm/amd/display/dc/core/dc_stream.c | 13 +++- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 3 +- .../dc/resource/dcn35/dcn35_resource.c | 10 ++- .../dc/resource/dcn35/dcn35_resource.h | 1 + .../dc/resource/dcn351/dcn351_resource.c | 10 ++- .../dc/resource/dcn36/dcn36_resource.c | 4 +- .../dc/resource/dcn401/dcn401_resource.c | 30 ++++++-- .../dc/resource/dcn42/dcn42_resource.c | 25 +++++-- 14 files changed, 169 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c index e46f8ce41d87..8ba9b4f56f87 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c @@ -53,11 +53,30 @@ inline void dc_assert_fp_enabled(void) { int depth; - depth = __this_cpu_read(fpu_recursion_depth); + depth = this_cpu_read(fpu_recursion_depth); ASSERT(depth >= 1); } +/** + * dc_assert_fp_enabled - Check if FPU protection is enabled + * + * This function tells if the code is already under FPU protection or not. A + * function that works as an API for a set of FPU operations can use this + * function for checking if the caller invoked it after DC_FP_START(). For + * example, take a look at dcn20_fpu.c file. + * + * Similar to dc_assert_fp_enabled, but does not assert, returns status instead. + */ +inline bool dc_is_fp_enabled(void) +{ + int depth; + + depth = this_cpu_read(fpu_recursion_depth); + + return (depth >= 1); +} + /** * dc_fpu_begin - Enables FPU protection * @function_name: A string containing the function name for debug purposes @@ -77,7 +96,7 @@ void dc_fpu_begin(const char *function_name, const int line) WARN_ON_ONCE(!in_task()); preempt_disable(); - depth = __this_cpu_inc_return(fpu_recursion_depth); + depth = this_cpu_inc_return(fpu_recursion_depth); if (depth == 1) { BUG_ON(!kernel_fpu_available()); kernel_fpu_begin(); @@ -100,7 +119,7 @@ void dc_fpu_end(const char *function_name, const int line) { int depth; - depth = __this_cpu_dec_return(fpu_recursion_depth); + depth = this_cpu_dec_return(fpu_recursion_depth); if (depth == 0) { kernel_fpu_end(); } else { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.h b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.h index 4e921632bc4e..5e95419d3798 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.h @@ -28,15 +28,30 @@ #define __DC_FPU_H__ void dc_assert_fp_enabled(void); +bool dc_is_fp_enabled(void); void dc_fpu_begin(const char *function_name, const int line); void dc_fpu_end(const char *function_name, const int line); #ifndef _LINUX_FPU_COMPILATION_UNIT #define DC_FP_START() dc_fpu_begin(__func__, __LINE__) #define DC_FP_END() dc_fpu_end(__func__, __LINE__) +#ifdef CONFIG_DRM_AMD_DC_FP +#define DC_RUN_WITH_PREEMPTION_ENABLED(code) \ + do { \ + bool dc_fp_enabled = dc_is_fp_enabled(); \ + if (dc_fp_enabled) \ + DC_FP_END(); \ + code; \ + if (dc_fp_enabled) \ + DC_FP_START(); \ + } while (0) +#else +#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code +#endif // !CONFIG_DRM_AMD_DC_FP #else #define DC_FP_START() BUILD_BUG() #define DC_FP_END() BUILD_BUG() -#endif +#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code +#endif // !_LINUX_FPU_COMPILATION_UNIT #endif /* __DC_FPU_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c index f2a716e1e732..4ad09b877b6e 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c @@ -421,10 +421,8 @@ static void dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) clk_mgr_base->bw_params->dc_mode_softmax_memclk = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK); /* Refresh bounding box */ - DC_FP_START(); clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box( clk_mgr->base.ctx->dc, clk_mgr_base->bw_params); - DC_FP_END(); } static bool dcn3_is_smu_present(struct clk_mgr *clk_mgr_base) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 7da7b41bd092..36d0c1e2014d 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -1059,11 +1059,9 @@ static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) if (!clk_mgr->dpm_present) dcn32_patch_dpm_table(clk_mgr_base->bw_params); - DC_FP_START(); /* Refresh bounding box */ clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box( clk_mgr->base.ctx->dc, clk_mgr_base->bw_params); - DC_FP_END(); } static bool dcn32_are_clock_states_equal(struct dc_clocks *a, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index e55ffdade662..2f938379aec7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1096,11 +1096,8 @@ static bool dc_construct(struct dc *dc, #ifdef CONFIG_DRM_AMD_DC_FP dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present; - if (dc->res_pool->funcs->update_bw_bounding_box) { - DC_FP_START(); + if (dc->res_pool->funcs->update_bw_bounding_box) dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); - DC_FP_END(); - } dc->soc_and_ip_translator = dc_create_soc_and_ip_translator(dc_ctx->dce_version); if (!dc->soc_and_ip_translator) goto fail; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c b/drivers/gpu/drm/amd/display/dc/core/dc_state.c index 2de8ef4a58ec..4b2d5a174fa9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c @@ -205,19 +205,33 @@ struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *p state->power_source = params ? params->power_source : DC_POWER_SOURCE_AC; #ifdef CONFIG_DRM_AMD_DC_FP + bool status; + if (dc->debug.using_dml2) { - if (!dml2_create(dc, &dc->dml2_options, &state->bw_ctx.dml2)) { + DC_FP_START(); + status = dml2_create(dc, &dc->dml2_options, &state->bw_ctx.dml2); + DC_FP_END(); + + if (!status) { dc_state_release(state); return NULL; } - if (dc->caps.dcmode_power_limits_present && !dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source)) { - dc_state_release(state); - return NULL; + if (dc->caps.dcmode_power_limits_present) { + bool status; + + DC_FP_START(); + status = dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source); + DC_FP_END(); + + if (!status) { + dc_state_release(state); + return NULL; + } } - } -#endif + } +#endif // CONFIG_DRM_AMD_DC_FP kref_init(&state->refcount); return state; @@ -235,14 +249,20 @@ void dc_state_copy(struct dc_state *dst_state, struct dc_state *src_state) #ifdef CONFIG_DRM_AMD_DC_FP dst_state->bw_ctx.dml2 = dst_dml2; - if (src_state->bw_ctx.dml2) + if (src_state->bw_ctx.dml2) { + DC_FP_START(); dml2_copy(dst_state->bw_ctx.dml2, src_state->bw_ctx.dml2); + DC_FP_END(); + } dst_state->bw_ctx.dml2_dc_power_source = dst_dml2_dc_power_source; - if (src_state->bw_ctx.dml2_dc_power_source) - dml2_copy(dst_state->bw_ctx.dml2_dc_power_source, src_state->bw_ctx.dml2_dc_power_source); -#endif + if (src_state->bw_ctx.dml2_dc_power_source) { + DC_FP_START(); + dml2_copy(dst_state->bw_ctx.dml2_dc_power_source, src_state->bw_ctx.dml2_dc_power_source); + DC_FP_END(); + } +#endif // CONFIG_DRM_AMD_DC_FP /* context refcount should not be overridden */ dst_state->refcount = refcount; } @@ -259,22 +279,35 @@ struct dc_state *dc_state_create_copy(struct dc_state *src_state) dc_state_copy_internal(new_state, src_state); #ifdef CONFIG_DRM_AMD_DC_FP + bool status; + new_state->bw_ctx.dml2 = NULL; new_state->bw_ctx.dml2_dc_power_source = NULL; - if (src_state->bw_ctx.dml2 && - !dml2_create_copy(&new_state->bw_ctx.dml2, src_state->bw_ctx.dml2)) { - dc_state_release(new_state); - return NULL; - } + if (src_state->bw_ctx.dml2) { + DC_FP_START(); + status = dml2_create_copy(&new_state->bw_ctx.dml2, src_state->bw_ctx.dml2); + DC_FP_END(); - if (src_state->bw_ctx.dml2_dc_power_source && - !dml2_create_copy(&new_state->bw_ctx.dml2_dc_power_source, src_state->bw_ctx.dml2_dc_power_source)) { - dc_state_release(new_state); - return NULL; + if (!status) { + dc_state_release(new_state); + return NULL; + } } -#endif + + if (src_state->bw_ctx.dml2_dc_power_source) { + DC_FP_START(); + status = dml2_create_copy(&new_state->bw_ctx.dml2_dc_power_source, + src_state->bw_ctx.dml2_dc_power_source); + DC_FP_END(); + + if (!status) { + dc_state_release(new_state); + return NULL; + } + } +#endif // CONFIG_DRM_AMD_DC_FP kref_init(&new_state->refcount); return new_state; @@ -352,11 +385,13 @@ static void dc_state_free(struct kref *kref) dc_state_destruct(state); #ifdef CONFIG_DRM_AMD_DC_FP + DC_FP_START(); dml2_destroy(state->bw_ctx.dml2); state->bw_ctx.dml2 = 0; dml2_destroy(state->bw_ctx.dml2_dc_power_source); state->bw_ctx.dml2_dc_power_source = 0; + DC_FP_END(); #endif kvfree(state); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 87ecef6e699f..473fe959f5c7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -42,6 +42,13 @@ #define MAX(x, y) ((x > y) ? x : y) #endif +#include "dc_fpu.h" + +#if !defined(DC_RUN_WITH_PREEMPTION_ENABLED) +#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code +#endif // !DC_RUN_WITH_PREEMPTION_ENABLED + + /******************************************************************************* * Private functions ******************************************************************************/ @@ -170,12 +177,14 @@ struct dc_stream_state *dc_create_stream_for_sink( if (sink == NULL) goto fail; - stream = kzalloc(sizeof(struct dc_stream_state), GFP_ATOMIC); + DC_RUN_WITH_PREEMPTION_ENABLED(stream = kzalloc(sizeof(struct dc_stream_state), GFP_ATOMIC)); if (stream == NULL) goto fail; - stream->update_scratch = kzalloc((int32_t) dc_update_scratch_space_size(), GFP_ATOMIC); + DC_RUN_WITH_PREEMPTION_ENABLED(stream->update_scratch = + kzalloc((int32_t) dc_update_scratch_space_size(), + GFP_ATOMIC)); if (stream->update_scratch == NULL) goto fail; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index a11dd9dd703b..f28a522ea6cd 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -363,8 +363,7 @@ void dcn401_init_hw(struct dc *dc) || res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000 != current_dchub_ref_freq) { /* update bounding box if FAMS2 disabled, or if dchub clk has changed */ if (dc->clk_mgr) - dc->res_pool->funcs->update_bw_bounding_box(dc, - dc->clk_mgr->bw_params); + dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); } } } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c index 2d8a5f157988..e87feb2d1fa8 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c @@ -1741,9 +1741,11 @@ static enum dc_status dcn35_validate_bandwidth(struct dc *dc, { bool out = false; + DC_FP_START(); out = dml2_validate(dc, context, context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, validate_mode); + DC_FP_END(); if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; @@ -1777,6 +1779,12 @@ static int populate_dml_pipes_from_context_fpu(struct dc *dc, return ret; } +void dcn35_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) +{ + DC_FP_START(); + dcn35_update_bw_bounding_box_fpu(dc, bw_params); + DC_FP_END(); +} static struct resource_funcs dcn35_res_pool_funcs = { .destroy = dcn35_destroy_resource_pool, .link_enc_create = dcn35_link_encoder_create, @@ -1798,7 +1806,7 @@ static struct resource_funcs dcn35_res_pool_funcs = { .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, - .update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu, + .update_bw_bounding_box = dcn35_update_bw_bounding_box, .patch_unknown_plane_state = dcn35_patch_unknown_plane_state, .get_panel_config_defaults = dcn35_get_panel_config_defaults, .get_preferred_eng_id_dpia = dcn35_get_preferred_eng_id_dpia, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h index 9c56ae76e0c7..6c2c61c711b9 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h @@ -312,4 +312,5 @@ struct resource_pool *dcn35_create_resource_pool( #define DPP_REG_LIST_DCN35_RI(id)\ DPP_REG_LIST_DCN30_COMMON_RI(id) +void dcn35_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); #endif /* _DCN35_RESOURCE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c index 9ed3d4879f76..c3454755a40f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c @@ -1721,9 +1721,11 @@ static enum dc_status dcn351_validate_bandwidth(struct dc *dc, { bool out = false; + DC_FP_START(); out = dml2_validate(dc, context, context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, validate_mode); + DC_FP_END(); if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; @@ -1750,6 +1752,12 @@ static int populate_dml_pipes_from_context_fpu(struct dc *dc, } +static void dcn351_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) +{ + DC_FP_START(); + dcn351_update_bw_bounding_box_fpu(dc, bw_params); + DC_FP_END(); +} static struct resource_funcs dcn351_res_pool_funcs = { .destroy = dcn351_destroy_resource_pool, .link_enc_create = dcn35_link_encoder_create, @@ -1771,7 +1779,7 @@ static struct resource_funcs dcn351_res_pool_funcs = { .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, - .update_bw_bounding_box = dcn351_update_bw_bounding_box_fpu, + .update_bw_bounding_box = dcn351_update_bw_bounding_box, .patch_unknown_plane_state = dcn35_patch_unknown_plane_state, .get_panel_config_defaults = dcn35_get_panel_config_defaults, .get_preferred_eng_id_dpia = dcn351_get_preferred_eng_id_dpia, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c index d849d9eeb121..d8ec832940cb 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c @@ -1728,9 +1728,11 @@ static enum dc_status dcn35_validate_bandwidth(struct dc *dc, { bool out = false; + DC_FP_START(); out = dml2_validate(dc, context, context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, validate_mode); + DC_FP_END(); if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; @@ -1778,7 +1780,7 @@ static struct resource_funcs dcn36_res_pool_funcs = { .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, - .update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu, + .update_bw_bounding_box = dcn35_update_bw_bounding_box, .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, .get_panel_config_defaults = dcn35_get_panel_config_defaults, .get_preferred_eng_id_dpia = dcn36_get_preferred_eng_id_dpia, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index 78bb1def9a0c..5a3684307c6b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -1647,8 +1647,10 @@ static struct dc_cap_funcs cap_funcs = { .get_subvp_en = dcn32_subvp_in_use, }; -static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) +static void dcn401_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) { + dc_assert_fp_enabled(); + /* re-calculate the available MALL size if required */ if (bw_params->num_channels > 0) { dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall( @@ -1657,17 +1659,19 @@ static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; } - DC_FP_START(); - if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2) dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source) dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source); +} +static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) +{ + DC_FP_START(); + dcn401_update_bw_bounding_box_fpu(dc, bw_params); DC_FP_END(); } - enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state) { plane_state->tiling_info.gfxversion = DcGfxAddr3; @@ -1692,10 +1696,13 @@ enum dc_status dcn401_validate_bandwidth(struct dc *dc, } } - if (dc->debug.using_dml2) + if (dc->debug.using_dml2) { + DC_FP_START(); status = dml2_validate(dc, context, context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; + DC_FP_END(); + } if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_OK && dc_state_is_subvp_in_use(context)) { /* check new stream configuration still supports cursor if subvp used */ @@ -1714,10 +1721,13 @@ enum dc_status dcn401_validate_bandwidth(struct dc *dc, if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_FAIL_HW_CURSOR_SUPPORT) { /* attempt to validate again with subvp disabled due to cursor */ - if (dc->debug.using_dml2) + if (dc->debug.using_dml2) { + DC_FP_START(); status = dml2_validate(dc, context, context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; + DC_FP_END(); + } } return status; @@ -1726,9 +1736,13 @@ enum dc_status dcn401_validate_bandwidth(struct dc *dc, void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context) { - if (dc->debug.using_dml21) + if (dc->debug.using_dml21) { + DC_FP_START(); dml2_prepare_mcache_programming(dc, context, - context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2); + context->power_source == DC_POWER_SOURCE_DC ? + context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2); + DC_FP_END(); + } } static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c index 9d6a989d6dd2..b9532ebcced4 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c @@ -1696,37 +1696,50 @@ static void dcn42_destroy_resource_pool(struct resource_pool **pool) static struct dc_cap_funcs cap_funcs = { .get_dcc_compression_cap = dcn20_get_dcc_compression_cap}; -static void dcn42_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) +static void dcn42_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) { - DC_FP_START(); + dc_assert_fp_enabled(); + if (dc->current_state && dc->current_state->bw_ctx.dml2) dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); - DC_FP_END(); } +static void dcn42_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) +{ + DC_FP_START(); + dcn42_update_bw_bounding_box_fpu(dc, bw_params); + DC_FP_END(); +} enum dc_status dcn42_validate_bandwidth(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode) { bool out = false; + DC_FP_START(); + out = dml2_validate(dc, context, context->bw_ctx.dml2, validate_mode); - DC_FP_START(); + if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) { /*not required for mode enumeration*/ dcn42_decide_zstate_support(dc, context); } + DC_FP_END(); + return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; } void dcn42_prepare_mcache_programming(struct dc *dc, struct dc_state *context) { - if (dc->debug.using_dml21) + if (dc->debug.using_dml21) { + DC_FP_START(); dml2_prepare_mcache_programming(dc, context, context->power_source == DC_POWER_SOURCE_DC ? - context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2); + context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2); + DC_FP_END(); + } } /* Create a minimal link encoder object not associated with a particular * physical connector. -- 2.43.0
