On Thu, Apr 30, 2026 at 12:29 PM Jesse Zhang <[email protected]> wrote:
>
> From: "David (Ming Qiang) Wu" <[email protected]>
>
> Use it to get the doorbell range and aggregated doorbell enablement
> and offset. This patch only supports VCN for now.
>
> V2 - drop VPE and use vcn.agdb_offset saved in
> umsch_mm_agdb_index_init() (suggested by Alex)
>
> Signed-off-by: David (Ming Qiang) Wu <[email protected]>
> Reviewed-by: Alex Deucher <[email protected]>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 18 ++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 1 +
> include/uapi/drm/amdgpu_drm.h | 13 +++++++++++++
> 3 files changed, 32 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index d88e4994c8c1..a3beeff800bf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -1425,6 +1425,24 @@ int amdgpu_info_ioctl(struct drm_device *dev, void
> *data, struct drm_file *filp)
> return -EINVAL;
> }
> }
> + case AMDGPU_INFO_DOORBELL: {
> + struct drm_amdgpu_info_doorbell doorbell_info = {};
> + /* note: may need to check asic_type */
> + switch (info->query_hw_ip.type) {
> + case AMDGPU_HW_IP_VCN_ENC:
> + if (adev->agdb_bo) {
I think this IOCTL should return an error adev->agdb_bo is NULL. We
probably also need a per-IP flag to determine if the aggregated
doorbell is required or not. That way we can easily support other IP
versions that may not require the aggregated doorbell.
> + doorbell_info.agdb_enable = 1;
> + doorbell_info.agdb_offset =
> adev->vcn.agdb_offset;
> + }
> + doorbell_info.index_start =
> adev->doorbell_index.vcn.vcn_ring0_1 << 1;
> + doorbell_info.index_end =
> (adev->doorbell_index.vcn.vcn_ring6_7 << 1) + 1;
> + break;
> + default:
> + return -EINVAL;
> + }
> + return copy_to_user(out, &doorbell_info,
> + min((size_t)size, sizeof(doorbell_info)))
> ? -EFAULT : 0;
> + }
> default:
> DRM_DEBUG_KMS("Invalid request %d\n", info->query);
> return -EINVAL;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> index 82624b44e661..f07920594295 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> @@ -368,6 +368,7 @@ struct amdgpu_vcn {
> struct mutex workload_profile_mutex;
> u32 reg_count;
> const struct amdgpu_hwip_reg_entry *reg_list;
> + uint32_t agdb_offset;
> };
>
> struct amdgpu_fw_shared_rb_ptrs_struct {
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index 062ae4741fd6..3ffdd2f8c418 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
I'd split this part out as a separate patch.
Alex
> @@ -1276,6 +1276,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
> #define AMDGPU_INFO_GPUVM_FAULT 0x23
> /* query FW object size and alignment */
> #define AMDGPU_INFO_UQ_FW_AREAS 0x24
> +/* query doorbell info */
> +#define AMDGPU_INFO_DOORBELL 0x25
>
> #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
> #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
> @@ -1677,6 +1679,17 @@ struct drm_amdgpu_info_uq_metadata {
> #define AMDGPU_FAMILY_GC_11_5_4 154 /* GC 11.5.4 */
> #define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */
>
> +/* for AMDGPU_INFO_DOORBELL query */
> +struct drm_amdgpu_info_doorbell {
> + __u32 index_start;
> + /* could be equal to index_start */
> + __u32 index_end;
> + /* aggregated doorbell, 0 for disable */
> + __u32 agdb_enable;
> + /* if agdb_enable, it is a value in [index_start, index_end] */
> + __u32 agdb_offset;
> +};
> +
> #if defined(__cplusplus)
> }
> #endif
> --
> 2.49.0
>
