From: Gaghik Khachatrian <[email protected]> [Why] Unreachable Code; Copy Constructor Deleted; Local Declaration Hides Parameter; Local Declaration Hides Outer Scope; Uninitialized or Suspicious Memory Use.
[How] - Removed or refactored unreachable code paths - Ensured proper copy constructors in C++ classes - Renamed local variables that shadowed function parameters - Renamed inner loop/block variables to avoid shadowing outer scope Fixed in 8 files across several FPU layers Also fixed in color_gamma and cs_funcs modules - Reordered guard conditions to validate pipe type before accessing stream - Ensures safe memory access patterns in DC DMUB service layer All changes maintain backward compatibility and preserve functional behavior. Reviewed-by: Dillon Varone <[email protected]> Signed-off-by: Gaghik Khachatrian <[email protected]> Signed-off-by: James Lin <[email protected]> --- drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +++--- .../gpu/drm/amd/display/dc/core/dc_state.c | 6 ++-- .../gpu/drm/amd/display/dc/core/dc_stream.c | 4 +-- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 3 +- .../dc/dml/dcn21/display_mode_vba_21.c | 8 +++--- .../drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 4 +-- .../amd/display/dc/dml/dcn314/dcn314_fpu.c | 10 +++---- .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 13 +++++---- .../drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 10 +++---- .../amd/display/dc/dml/dcn351/dcn351_fpu.c | 10 +++---- .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 4 +-- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 3 ++ .../amd/display/modules/color/color_gamma.c | 28 +++++++++---------- 13 files changed, 57 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 1e178becf949..0e9ea06d7297 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -4976,7 +4976,7 @@ static void commit_planes_for_stream(struct dc *dc, if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && should_update_pipe_for_stream(context, pipe_ctx, stream)) { - struct dc_stream_status *stream_status = NULL; + struct dc_stream_status *pipe_stream_status = NULL; if (!pipe_ctx->plane_state) continue; @@ -4985,12 +4985,12 @@ static void commit_planes_for_stream(struct dc *dc, if (update_type == UPDATE_TYPE_FAST) continue; - stream_status = + pipe_stream_status = stream_get_status(context, pipe_ctx->stream); - if (dc->hwss.apply_ctx_for_surface && stream_status) + if (dc->hwss.apply_ctx_for_surface && pipe_stream_status) dc->hwss.apply_ctx_for_surface( - dc, pipe_ctx->stream, stream_status->plane_count, context); + dc, pipe_ctx->stream, pipe_stream_status->plane_count, context); } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c b/drivers/gpu/drm/amd/display/dc/core/dc_state.c index 0cc26f750586..1f183ae85a3f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c @@ -218,13 +218,13 @@ struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *p } if (dc->caps.dcmode_power_limits_present) { - bool status; + bool dc_power_status; DC_FP_START(); - status = dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source); + dc_power_status = dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source); DC_FP_END(); - if (!status) { + if (!dc_power_status) { dc_state_release(state); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 438e6415db6d..d4c32c945606 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -602,7 +602,7 @@ bool dc_stream_add_writeback(struct dc *dc, if (dc->hwss.enable_writeback) { struct dc_stream_status *stream_status = dc_stream_get_status(stream); - struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; + dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; if (stream_status) dwb->otg_inst = stream_status->primary_otg_inst; } @@ -614,7 +614,7 @@ bool dc_stream_add_writeback(struct dc *dc, /* enable writeback */ if (dc->hwss.enable_writeback) { - struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; + dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; if (dwb->funcs->is_enabled(dwb)) { /* writeback pipe already enabled, only need to update */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index af487fa0db03..ea0210216d9e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -488,12 +488,11 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; - if (!resource_is_pipe_type(pipe, OTG_MASTER)) + if (!resource_is_pipe_type(pipe, OTG_MASTER) || !pipe->stream) continue; stream_status = dc_state_get_stream_status(context, pipe->stream); if (stream_status && stream_status->fpo_in_use) { - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; uint8_t min_refresh_in_hz; min_refresh_in_hz = (uint8_t)((pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c index df23ced2ff5a..3ff71751db1e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c @@ -4809,14 +4809,14 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.MaximumReadBandwidthWithoutPrefetch = 0.0; mode_lib->vba.MaximumReadBandwidthWithPrefetch = 0.0; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { - unsigned int m; + unsigned int cursor_idx; locals->cursor_bw[k] = 0; locals->cursor_bw_pre[k] = 0; - for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) { - locals->cursor_bw[k] = mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] + for (cursor_idx = 0; cursor_idx < mode_lib->vba.NumberOfCursors[k]; cursor_idx++) { + locals->cursor_bw[k] = mode_lib->vba.CursorWidth[k][cursor_idx] * mode_lib->vba.CursorBPP[k][cursor_idx] / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; - locals->cursor_bw_pre[k] = mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] + locals->cursor_bw_pre[k] = mode_lib->vba.CursorWidth[k][cursor_idx] * mode_lib->vba.CursorBPP[k][cursor_idx] / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * locals->VRatioPreY[i][j][k]; } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c index 79c567b6806e..0ba388c6aec1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c @@ -721,9 +721,9 @@ void dcn3_fpu_build_wm_range_table(struct clk_mgr *base) base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF; } -void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *dcn3_0_ip) +void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *soc_bb) { - (void)dcn3_0_ip; + (void)soc_bb; dc_assert_fp_enabled(); if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c index 29334772408e..2f9ae79da731 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c @@ -410,15 +410,15 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c context->bw_ctx.dml.ip.odm_combine_4to1_supported = true; for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i]; - if (!pipe->stream) + if (!cur_pipe->stream) continue; - if (pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine && - pipe->stream->apply_seamless_boot_optimization) { + if (cur_pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine && + cur_pipe->stream->apply_seamless_boot_optimization) { - if (pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) { + if (cur_pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) { context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1; break; } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index a97e38aa7fed..03e49d298a85 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -2216,7 +2216,7 @@ bool dcn32_internal_validate_bw(struct dc *dc, if (repopulate_pipes) { int flag_max_mpc_comb = vba->maxMpcComb; int flag_vlevel = vlevel; - int i; + int j; pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); if (!dc->config.enable_windowed_mpo_odm) @@ -2231,19 +2231,20 @@ bool dcn32_internal_validate_bw(struct dc *dc, dm_prefetch_support_uclk_fclk_and_stutter_if_possible; vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); + const int num_states = (int)context->bw_ctx.dml.soc.num_states; - if (vlevel == context->bw_ctx.dml.soc.num_states) { + if (vlevel == num_states) { /* failed after DET size changes */ goto validate_fail; } else if (flag_max_mpc_comb == 0 && flag_max_mpc_comb != context->bw_ctx.dml.vba.maxMpcComb) { /* check the context constructed with pipe split flags is still valid*/ bool flags_valid = false; - for (i = flag_vlevel; i < (int)context->bw_ctx.dml.soc.num_states; i++) { - if (vba->ModeSupport[i][flag_max_mpc_comb]) { + for (j = flag_vlevel; j < (int)context->bw_ctx.dml.soc.num_states; j++) { + if (vba->ModeSupport[j][flag_max_mpc_comb]) { vba->maxMpcComb = flag_max_mpc_comb; - vba->VoltageLevel = i; - vlevel = i; + vba->VoltageLevel = j; + vlevel = j; flags_valid = true; break; } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c index bef2b0bcfcf0..c15fbc18bfdf 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c @@ -551,16 +551,16 @@ int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc, } for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i]; - if (!pipe->stream) + if (!cur_pipe->stream) continue; - if (pipe->stream->signal == SIGNAL_TYPE_EDP && + if (cur_pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine && - pipe->stream->apply_seamless_boot_optimization) { + cur_pipe->stream->apply_seamless_boot_optimization) { - if (pipe->stream->apply_boot_odm_mode == + if (cur_pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) { context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c index 9545d946215b..6552b26de845 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c @@ -583,16 +583,16 @@ int dcn351_populate_dml_pipes_from_context_fpu(struct dc *dc, } for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i]; - if (!pipe->stream) + if (!cur_pipe->stream) continue; - if (pipe->stream->signal == SIGNAL_TYPE_EDP && + if (cur_pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine && - pipe->stream->apply_seamless_boot_optimization) { + cur_pipe->stream->apply_seamless_boot_optimization) { - if (pipe->stream->apply_boot_odm_mode == + if (cur_pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) { context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 169f34ea75b1..2c2fa320df40 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -3636,8 +3636,8 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) if (dc->hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied) { struct dce_hwseq *hwseq = dc->hwseq; - struct timing_generator *tg = dc->res_pool->timing_generators[0]; - unsigned int cur_frame = tg->funcs->get_frame_count(tg); + struct timing_generator *wa_tg = dc->res_pool->timing_generators[0]; + unsigned int cur_frame = wa_tg->funcs->get_frame_count(wa_tg); if (cur_frame != hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame) { struct hubbub *hubbub = dc->res_pool->hubbub; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 55a672b4e886..204f11b784bb 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1952,6 +1952,9 @@ void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx) * This is meant to work around a known HW issue where VREADY will cancel the pending 3DLUT_ENABLE signal regardless * of whether OTG lock is currently being held or not. */ + if (!pipe_ctx) + return; + struct pipe_ctx *wa_pipes[MAX_PIPES] = { NULL }; struct pipe_ctx *odm_pipe, *mpc_pipe; int i, wa_pipe_ct = 0; diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c index b79ca7a2eedc..2ac01083de88 100644 --- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c +++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c @@ -690,7 +690,7 @@ static bool find_software_points( static bool build_custom_gamma_mapping_coefficients_worker( const struct dc_gamma *ramp, struct pixel_gamma_point *coeff, - const struct hw_x_point *coordinates_x, + const struct hw_x_point *hw_coordinates_x, const struct gamma_pixel *axis_x, enum channel_name channel, uint32_t number_of_points) @@ -712,11 +712,11 @@ static bool build_custom_gamma_mapping_coefficients_worker( struct fixed31_32 right_pos; if (channel == CHANNEL_NAME_RED) - coord_x = coordinates_x[i].regamma_y_red; + coord_x = hw_coordinates_x[i].regamma_y_red; else if (channel == CHANNEL_NAME_GREEN) - coord_x = coordinates_x[i].regamma_y_green; + coord_x = hw_coordinates_x[i].regamma_y_green; else - coord_x = coordinates_x[i].regamma_y_blue; + coord_x = hw_coordinates_x[i].regamma_y_blue; if (!find_software_points( ramp, axis_x, coord_x, channel, @@ -1539,11 +1539,11 @@ static void build_evenly_distributed_points( } static inline void copy_rgb_regamma_to_coordinates_x( - struct hw_x_point *coordinates_x, + struct hw_x_point *hw_coordinates_x, uint32_t hw_points_num, const struct pwl_float_data_ex *rgb_ex) { - struct hw_x_point *coords = coordinates_x; + struct hw_x_point *coords = hw_coordinates_x; uint32_t i = 0; const struct pwl_float_data_ex *rgb_regamma = rgb_ex; @@ -1562,7 +1562,7 @@ static bool calculate_interpolated_hardware_curve( const struct dc_gamma *ramp, struct pixel_gamma_point *coeff128, struct pwl_float_data *rgb_user, - const struct hw_x_point *coordinates_x, + const struct hw_x_point *hw_coordinates_x, const struct gamma_pixel *axis_x, uint32_t number_of_points, struct dc_transfer_func_distributed_points *tf_pts) @@ -1575,7 +1575,7 @@ static bool calculate_interpolated_hardware_curve( for (i = 0; i < 3; i++) { if (!build_custom_gamma_mapping_coefficients_worker( - ramp, coeff128, coordinates_x, axis_x, i, + ramp, coeff128, hw_coordinates_x, axis_x, i, number_of_points)) return false; } @@ -1789,14 +1789,14 @@ bool mod_color_calculate_degamma_params(struct dc_color_caps *dc_caps, if (input_tf->tf == TRANSFER_FUNCTION_PQ) { /* just copy current rgb_regamma into tf_pts */ struct pwl_float_data_ex *curvePt = curve; - int i = 0; + int j = 0; - while (i <= MAX_HW_POINTS) { - tf_pts->red[i] = curvePt->r; - tf_pts->green[i] = curvePt->g; - tf_pts->blue[i] = curvePt->b; + while (j <= MAX_HW_POINTS) { + tf_pts->red[j] = curvePt->r; + tf_pts->green[j] = curvePt->g; + tf_pts->blue[j] = curvePt->b; ++curvePt; - ++i; + ++j; } } else { // clamps to 0-1 -- 2.43.0
