From: Charlene Liu <[email protected]> [Why & How] this is to force ODM 2:1 on single eDP to lower dispclk/dppclk.
Reviewed-by: Dillon Varone <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: James Lin <[email protected]> --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../dc/resource/dcn42/dcn42_resource.c | 4 ++++ .../dc/resource/dcn42/dcn42_resource_fpu.c | 22 +++++++++++++++++++ .../dc/resource/dcn42/dcn42_resource_fpu.h | 2 +- 4 files changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e5933e3a8206..30ff7f1b9513 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1219,6 +1219,7 @@ struct dc_debug_options { unsigned int force_vmin_threshold; bool enable_otg_frame_sync_pwa; unsigned int min_deep_sleep_dcfclk_khz; + unsigned int force_odm2to1_for_edp_pixclk_mhz; }; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c index 57c6e81280bc..01a7639da80b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c @@ -765,6 +765,7 @@ static const struct dc_debug_options debug_defaults_drv = { .min_deep_sleep_dcfclk_khz = 8000, .replay_skip_crtc_disabled = true, .psr_skip_crtc_disable = true, + .force_odm2to1_for_edp_pixclk_mhz = 550, // Force ODM 2to1 for eDP when pixel clock is above 550MHz }; static const struct dc_check_config config_defaults = { @@ -1721,9 +1722,12 @@ enum dc_status dcn42_validate_bandwidth(struct dc *dc, DC_FP_START(); + dcn42_decide_odm_override(dc, context); + out = dml2_validate(dc, context, context->bw_ctx.dml2, validate_mode); + if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) { /*not required for mode enumeration*/ dcn42_decide_zstate_support(dc, context); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c index 33b9775420d3..ee330559c233 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c @@ -45,3 +45,25 @@ void dcn42_decide_zstate_support(struct dc *dc, struct dc_state *context) context->bw_ctx.bw.dcn.clk.zstate_support = support; } + +bool dcn42_decide_odm_override(struct dc *dc, struct dc_state *context) +{ + bool odm_override = false; + + DC_LOGGER_INIT(dc->ctx->logger); + if (dc->ctx->dce_environment == DCE_ENV_DIAG) + return false; + + if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) { + + if (dc->debug.force_odm2to1_for_edp_pixclk_mhz != 0 && + context->streams[0]->timing.pix_clk_100hz > dc->debug.force_odm2to1_for_edp_pixclk_mhz * 10000) { + odm_override = true; + context->streams[0]->debug.force_odm_combine_segments = 2; + } + DC_LOG_SMU("odm_override: %d, eDP pixelclock: %d, force_odm2to1_for_edp_pixclk_mhz: %d\n", + odm_override, context->streams[0]->timing.pix_clk_100hz / 10000, dc->debug.force_odm2to1_for_edp_pixclk_mhz); + } + return odm_override; +} + diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h index e32103220507..aff7be777681 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h @@ -29,5 +29,5 @@ #include "core_types.h" void dcn42_decide_zstate_support(struct dc *dc, struct dc_state *context); - +bool dcn42_decide_odm_override(struct dc *dc, struct dc_state *context); #endif /* _DCN42_RESOURCE_FPU_H_ */ -- 2.43.0
