From: James Lin <[email protected]>
[why & how]
Some DCN4.2 related code is missing from upstream
Fixes: 66715fc0ecfd ("drm/amd/display: Sync dcn42 with DC 3.2.373")
Acked-by: ChiaHsuan Chung <[email protected]>
Reviewed-by: Roman Li <[email protected]>
Signed-off-by: James Lin <[email protected]>
---
.../drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 2 ++
.../gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c | 5 +++--
.../drm/amd/display/dc/resource/dcn42/dcn42_resource.c | 10 ++++------
.../drm/amd/display/dc/resource/dcn42/dcn42_resource.h | 7 +++++++
4 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
index d856a7a807b1..d01e5969a670 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
@@ -309,6 +309,8 @@ void dcn42_update_clocks(struct clk_mgr *clk_mgr_base,
}
// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch
to plus 4K monitor underflow.
+ if (new_clocks->dppclk_khz < 100000)
+ new_clocks->dppclk_khz = 100000;
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz,
clk_mgr->base.clks.dppclk_khz)) {
if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
index cbc20f214f9e..cabfac151940 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
@@ -470,9 +470,9 @@ static bool is_rmcm_3dlut_fl_supported(struct dc *dc, enum
dc_cm2_gpu_mem_size s
if (!dc->caps.color.mpc.rmcm_3d_lut_caps.dma_3d_lut)
return false;
if (size == DC_CM2_GPU_MEM_SIZE_171717)
- return
(dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_17);
+ return dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_17
!= 0u;
else if (size == DC_CM2_GPU_MEM_SIZE_333333)
- return
(dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33);
+ return dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33
!= 0u;
return false;
}
@@ -945,6 +945,7 @@ bool dcn42_set_mcm_luts(struct pipe_ctx *pipe_ctx,
void dcn42_hardware_release(struct dc *dc)
{
dcn35_hardware_release(dc);
+ dc_dmub_srv_release_hw(dc);
}
static int count_active_streams(const struct dc *dc)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
index 52a1996a654f..1fc457cec293 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
@@ -1520,6 +1520,10 @@ static void dcn42_resource_destruct(struct
dcn42_resource_pool *pool)
if (pool->base.pg_cntl != NULL)
dcn_pg_cntl_destroy(&pool->base.pg_cntl);
+
+ if (pool->base.replay != NULL)
+ dmub_replay_destroy(&pool->base.replay);
+
if (pool->base.dccg != NULL)
dcn_dccg_destroy(&pool->base.dccg);
@@ -1921,12 +1925,6 @@ static bool dcn42_resource_construct(
dc->caps.max_v_total = (1 << 15) - 1;
dc->caps.vtotal_limited_by_fp2 = true;
- dc->caps.seamless_odm = true;
- dc->caps.zstate_support = true;
- dc->caps.ips_support = true;
- dc->caps.max_v_total = (1 << 15) - 1;
- dc->caps.vtotal_limited_by_fp2 = true;
-
/* Color pipeline capabilities */
dc->caps.color.dpp.dcn_arch = 1;
dc->caps.color.dpp.input_lut_shared = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
index 60acf0e423d9..fe960542d7bd 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
@@ -456,6 +456,8 @@
SRI_ARR(OTG_V_SYNC_A, OTG, inst), \
SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \
SRI_ARR(OTG_CONTROL, OTG, inst), \
+ SRI_ARR(OTG_MASTER_EN, OTG, inst), \
+ SRI_ARR(OTG_LONG_VBLANK_STATUS, OTG, inst), \
SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \
SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst),
\
SRI_ARR(OTG_STEREO_STATUS, OTG, inst),
\
@@ -472,6 +474,11 @@
SRI_ARR(OTG_M_CONST_DTO0, OTG, inst),
\
SRI_ARR(OTG_M_CONST_DTO1, OTG, inst),
\
SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst),
\
+ SRI_ARR(OTG_COUNT_CONTROL, OTG, inst),
\
+ SRI_ARR(OTG_COUNT_RESET, OTG, inst),
\
+ SRI_ARR(OTG_CRC_SIG_BLUE_CONTROL_MASK, OTG, inst),
\
+ SRI_ARR(OTG_CRC_SIG_RED_GREEN_MASK, OTG, inst),
\
+ SRI_ARR(OTG_DRR_TIMING_INT_STATUS, OTG, inst),
\
SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),
\
SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),
\
SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),
\
--
2.43.0
