From: Leo Li <[email protected]> This series collects a few fixes targeting the intermittent flip_done timeouts that have been reported on a range of DCN systems (most notably NV3x+ DGPUs and some PSR-capable platforms).
The investigation pointed at two distinct root causes: 1. Cursor vblank events are delivered from the vstartup OTG interrupt, which HW can mask (see [2/3] for details). When that happens, no vblank event reaches userspace and the commit eventually times out. 2. PSR-capable systems can engage dynamic power-gating on HUBP, the HW block responsible for delivering the pflip interrupt. Programming a flip before HUBP fully exits DPG can mask the interrupt. Patch 1 reverts the 5s vbl offdelay workaround that was added for NV3x+ DGPUs, since the underlying issues are now addressed by patches 2 and 3. Patch 2 switches DCN vblank delivery from vstartup to the vline2 generic OTG interrupt. Unlike vstartup, vline interrupts cannot be masked while the OTG is active, so they are a reliable signal for delivering vblank events. Patch 3 adds a backup path for masked pflip interrupts on the newly introduced vline2 handler. Many thanks to the reporters who collaborated on these issues [1][2][3]; the bug seems to avoid driver devs. Your help with testing patches and collecting debug data was critical to these fixes! [1] https://gitlab.freedesktop.org/drm/amd/-/work_items/4141 [2] https://gitlab.freedesktop.org/drm/amd/-/work_items/3787 [3] https://lore.kernel.org/amd-gfx/[email protected]/ Changes since v1: * Include a revert [Patch 1/3] of the change that restored the 5s vbl offdelay * Fix vline2 irq_source [Patch 2/3] to map from crtc to otg index correctly * Add a fix [Patch 3/3] to address PSR exit race with flips Thanks, Leo Leo Li (3): Revert "drm/amd/display: Restore 5s vbl offdelay for NV3x+ DGPUs" drm/amd/display: Use vline2 interrupt on DCN instead of vstartup drm/amd/display: Check for flip completion in OTG interrupt handlers drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 248 ++++++++++++------ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 9 + .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 20 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 103 ++++++-- .../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h | 7 + .../display/amdgpu_dm/amdgpu_dm_irq_params.h | 8 + .../display/dc/irq/dcn10/irq_service_dcn10.c | 44 +++- .../display/dc/irq/dcn20/irq_service_dcn20.c | 43 ++- .../dc/irq/dcn201/irq_service_dcn201.c | 24 +- .../display/dc/irq/dcn21/irq_service_dcn21.c | 44 +++- .../display/dc/irq/dcn30/irq_service_dcn30.c | 44 +++- .../dc/irq/dcn302/irq_service_dcn302.c | 43 ++- .../dc/irq/dcn303/irq_service_dcn303.c | 24 +- .../display/dc/irq/dcn31/irq_service_dcn31.c | 44 +++- .../dc/irq/dcn314/irq_service_dcn314.c | 44 +++- .../dc/irq/dcn315/irq_service_dcn315.c | 44 +++- .../display/dc/irq/dcn32/irq_service_dcn32.c | 26 +- .../display/dc/irq/dcn35/irq_service_dcn35.c | 41 ++- .../dc/irq/dcn351/irq_service_dcn351.c | 43 ++- .../display/dc/irq/dcn36/irq_service_dcn36.c | 41 ++- .../dc/irq/dcn401/irq_service_dcn401.c | 25 +- .../display/dc/irq/dcn42/irq_service_dcn42.c | 26 +- .../gpu/drm/amd/display/dc/irq/irq_service.h | 18 ++ 24 files changed, 744 insertions(+), 271 deletions(-) -- 2.53.0
