On 6/12/26 15:48, Timur Kristóf wrote: > Hi Jiqian, > >>> Indeed I've seen similar issues on other GPUs, as I've been looking into >>> improving GPU recovery. >>> >>> Instead of forcing the HQD_ACTIVE to zero, I suggest to deactivate the HQD >>> before reset. We should introduce a gfx_v9_0_deactivate_hqd() function >>> similar to what gfx_v8_0_deactivate_hqd() is doing, and call that from >>> somewhere in gfx_v9_0_hw_fini() when disabling the compute queues. >> >> Make sense, that look like a more suitable place, I will try to move my >> sequences into gfx_v9_0_hw_fini() in next version. > > Sounds good. > >>> In fact, it looks like it already deactivates HQD, but only for the KIQ >>> and only when it isn't in reset or suspend. That looks wrong to me and >>> I think it should do that for all compute queues (in addition to the KIQ) >>> either unconditionally or before a mode2 reset. >> >> So, you think the if condition checks are not needed? >> if ((adev->flags & AMD_IS_APU) && amdgpu_in_reset(adev) && >> amdgpu_asic_reset_method(adev) == > AMD_RESET_METHOD_MODE2) >> Since I only reproduced and verified when mode2 on APU, I think keeping this >> check would be better. > > Yes, I think the checks may not be needed or need to be adjusted. I am not sure if removing the checks can cause new issues in other APUs or dGPUs that don't have this issue. Per our tests, GPUs that use Mode1 don't have this issue. Is disabling HQD harmless even for GPUs that are not experiencing this issue?
> Additionally, the same sequence needs to be repeated for every compute ring. Yes, I had done these for every compute ring. > >>> I don't have a Renoir APU yet but if you need help, I can try to see if I >>> can reproduce something like this on a Vega 10 dGPU. >> >> It seems Vega 10 dGPU uses Moed1 or BACO reset. I am not sure if it has the >> same issue. When you "see similar issues on other GPUs", are they all APUs? >> What's the gfx version? And what reset method they use. If they are not, I >> may find a same hardware as your to verify my changes. I tried other APU >> with gfx10, there is no this issue. > > You are correct that dGPUs don't use mode2 reset. I saw a similar issue while > working on a patch series to improve GFX IP block soft reset on GFX8. I am > testing that on a Carrizo APU as well as Fiji and Polaris 10 dGPUs. > > The problem I saw is very similar to yours: compute rings fail to resume > after > the reset and are "stuck". I managed to solve that by making sure the HQD is > deactivated before the reset and ensuring that the MQD is cleaned up after > the > reset. That's great, you already have solved the gfx8 issue. > > Best regards, > Timur > > > > > > > > -- Best regards, Jiqian Chen.
