On Tue, Jul 14, 2026 at 11:13 AM Christian König <[email protected]> wrote: > > > > On 7/14/26 17:03, Alex Deucher wrote: > > On Tue, Jul 14, 2026 at 9:46 AM Christian König > > <[email protected]> wrote: > >> > >> On 7/14/26 15:42, Alex Deucher wrote: > >>> On Tue, Jul 14, 2026 at 3:19 AM Christian König > >>> <[email protected]> wrote: > >>>> > >>>> On 7/13/26 20:27, Alex Deucher wrote: > >>>>> Use this interface to issue TLB invalidations using > >>>>> SDMA. > >>>> > >>>> Hui? What should that be good for? > >>> > >>> To use as a replacement for doing the invalidation using MES. > >> > >> We should already have that as workaround for the Navi 1x SDMA bug. > >> > >> I suggest to just move that code into a separate function instead. > >> > >> But the SDMA can't do PASID based invalidation and that is what we need > >> the MES for, so I'm not sure how useful that will be. > > > > The current gmc code doesn't do pasid based invalidation either. > > Everything ends up in gmc_vXX_0_flush_gpu_tlb() for each gmc version. > > Yeah, but that one shouldn't use the MES in the first place. We could use > direct register accesses here. > > Using the MES makes only sense if we invalidate per PASID. > > Why are we using the MES for per VMID invalidation?
gfxoff. We can't access the registers directly unless we disallow gfxoff. Alex > > Regards, > Christian. > > > > > Alex > > > >> > >> Regards, > >> Christian. > >> > >>> > >>> Alex > >>> > >>>> > >>>> Regards, > >>>> Christian. > >>>> > >>>>> > >>>>> Signed-off-by: Alex Deucher <[email protected]> > >>>>> --- > >>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 18 ++++++++++++++++++ > >>>>> 1 file changed, 18 insertions(+) > >>>>> > >>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h > >>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h > >>>>> index 4f4e56022c970..4ab92d287675a 100644 > >>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h > >>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h > >>>>> @@ -155,6 +155,23 @@ struct amdgpu_buffer_funcs { > >>>>> uint64_t dst_offset, > >>>>> /* number of byte to fill */ > >>>>> uint32_t byte_count); > >>>>> + > >>>>> + /* number of dw to reserve per operation */ > >>>>> + unsigned tlb_inv_num_dw; > >>>>> + > >>>>> + /* used for buffer clearing */ > >>>>> + void (*emit_tlb_inv)(struct amdgpu_device *adev, > >>>>> + struct amdgpu_ib *ib, > >>>>> + /* vmid to target */ > >>>>> + unsigned int vmid, > >>>>> + /* vmhub to target */ > >>>>> + u32 vmhub, > >>>>> + /* inv eng to target */ > >>>>> + u32 eng, > >>>>> + /* flush type */ > >>>>> + u32 flush_type, > >>>>> + /* XCC to target */ > >>>>> + u32 xcc_inst); > >>>>> }; > >>>>> > >>>>> int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t > >>>>> instance_id, > >>>>> @@ -162,6 +179,7 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device > >>>>> *adev, uint32_t instance_id, > >>>>> > >>>>> #define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) > >>>>> (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b), (t)) > >>>>> #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) > >>>>> (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) > >>>>> +#define amdgpu_emit_tlb_inv(adev, ib, v, h, e, f, x) > >>>>> (adev)->mman.buffer_funcs->emit_tlb_inv((adev), (ib), (v), (h), (e), > >>>>> (f), (x)) > >>>>> > >>>>> struct amdgpu_sdma_instance * > >>>>> amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring); > >>>> > >> >
