From: Alex Hung <[email protected]> [WHAT] amdgpu_dm_smu_write_watermarks_table() pushes fixed dcn watermark clock settings to the SMU on Navi1x. It belongs with the other dc-pplib bridge code, so move it out of amdgpu_dm.c into amdgpu_dm_pp_smu.c.
It is called from dm_resume(), so it becomes a plain exported function declared in amdgpu_dm_pp_smu.h (now included by amdgpu_dm.c) instead of STATIC_IFN_KUNIT in amdgpu_dm.h. Relocate its KUnit test from the amdgpu_dm suite to the amdgpu_dm_pp_smu suite. No functional change. Reviewed-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Fangzhi Zuo <[email protected]> Tested-by: Dan Wheeler <[email protected]> --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 53 +------------------ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 - .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 52 ++++++++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.h | 3 ++ .../amdgpu_dm/tests/amdgpu_dm_pp_smu_test.c | 20 +++++++ .../display/amdgpu_dm/tests/amdgpu_dm_test.c | 16 ------ 6 files changed, 76 insertions(+), 69 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c6b9cd1ce489..d49f0cd3b113 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -70,6 +70,7 @@ #include "amdgpu_dm_audio.h" #include "amdgpu_dm_dmub.h" #include "amdgpu_dm_connector.h" +#include "amdgpu_dm_pp_smu.h" #include "ivsrcid/ivsrcid_vislands30.h" @@ -1372,58 +1373,6 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend) drm_connector_list_iter_end(&iter); } -STATIC_IFN_KUNIT int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) -{ - int ret = 0; - - /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends - * on window driver dc implementation. - * For Navi1x, clock settings of dcn watermarks are fixed. the settings - * should be passed to smu during boot up and resume from s3. - * boot up: dc calculate dcn watermark clock settings within dc_create, - * dcn20_resource_construct - * then call pplib functions below to pass the settings to smu: - * smu_set_watermarks_for_clock_ranges - * smu_set_watermarks_table - * navi10_set_watermarks_table - * smu_write_watermarks_table - * - * For Renoir, clock settings of dcn watermark are also fixed values. - * dc has implemented different flow for window driver: - * dc_hardware_init / dc_set_power_state - * dcn10_init_hw - * notify_wm_ranges - * set_wm_ranges - * -- Linux - * smu_set_watermarks_for_clock_ranges - * renoir_set_watermarks_table - * smu_write_watermarks_table - * - * For Linux, - * dc_hardware_init -> amdgpu_dm_init - * dc_set_power_state --> dm_resume - * - * therefore, this function apply to navi10/12/14 but not Renoir - * * - */ - switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { - case IP_VERSION(2, 0, 2): - case IP_VERSION(2, 0, 0): - break; - default: - return 0; - } - - ret = amdgpu_dpm_write_watermarks_table(adev); - if (ret) { - drm_err(adev_to_drm(adev), "Failed to update WMTABLE!\n"); - return ret; - } - - return 0; -} -EXPORT_IF_KUNIT(amdgpu_dm_smu_write_watermarks_table); - static int dm_oem_i2c_hw_init(struct amdgpu_device *adev) { struct amdgpu_display_manager *dm = &adev->dm; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 617328497203..70220997cde9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -1157,7 +1157,6 @@ int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, struct dm_atomic_state *dm_atomic_get_new_state(struct drm_atomic_commit *state); void dm_atomic_destroy_state(struct drm_private_obj *obj, struct drm_private_state *state); -int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev); bool dm_should_update_native_cursor(struct drm_atomic_commit *state, struct drm_crtc *old_plane_crtc, struct drm_crtc *new_plane_crtc, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c index 8431e164a0db..3280bfadc6a8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c @@ -792,3 +792,55 @@ void dm_pp_get_funcs( } } EXPORT_IF_KUNIT(dm_pp_get_funcs); + +int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) +{ + int ret = 0; + + /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends + * on window driver dc implementation. + * For Navi1x, clock settings of dcn watermarks are fixed. the settings + * should be passed to smu during boot up and resume from s3. + * boot up: dc calculate dcn watermark clock settings within dc_create, + * dcn20_resource_construct + * then call pplib functions below to pass the settings to smu: + * smu_set_watermarks_for_clock_ranges + * smu_set_watermarks_table + * navi10_set_watermarks_table + * smu_write_watermarks_table + * + * For Renoir, clock settings of dcn watermark are also fixed values. + * dc has implemented different flow for window driver: + * dc_hardware_init / dc_set_power_state + * dcn10_init_hw + * notify_wm_ranges + * set_wm_ranges + * -- Linux + * smu_set_watermarks_for_clock_ranges + * renoir_set_watermarks_table + * smu_write_watermarks_table + * + * For Linux, + * dc_hardware_init -> amdgpu_dm_init + * dc_set_power_state --> dm_resume + * + * therefore, this function apply to navi10/12/14 but not Renoir + * * + */ + switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { + case IP_VERSION(2, 0, 2): + case IP_VERSION(2, 0, 0): + break; + default: + return 0; + } + + ret = amdgpu_dpm_write_watermarks_table(adev); + if (ret) { + drm_err(adev_to_drm(adev), "Failed to update WMTABLE!\n"); + return ret; + } + + return 0; +} +EXPORT_IF_KUNIT(amdgpu_dm_smu_write_watermarks_table); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.h index f918eb71f0d1..1d153d0e2f03 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.h @@ -11,6 +11,9 @@ struct amd_pp_display_configuration; struct pp_smu_wm_range_sets; struct dm_pp_wm_sets_with_clock_ranges_soc15; +struct amdgpu_device; + +int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev); #if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST) void build_pm_display_cfg(struct amd_pp_display_configuration *pm_display_cfg, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_pp_smu_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_pp_smu_test.c index 8d1d26bfcc16..fbd07af60230 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_pp_smu_test.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_pp_smu_test.c @@ -16,6 +16,7 @@ #include "amdgpu_mode.h" #include "amdgpu_dm.h" #include "amdgpu_dm_pp_smu.h" +#include "amdgpu_dm_kunit_test_helpers.h" /* ---- Stub DPM layer ---- */ @@ -2321,6 +2322,23 @@ static void dm_test_nv_get_uclk_dpm_states_fail(struct kunit *test) (int)PP_SMU_RESULT_FAIL); } +/* Tests for amdgpu_dm_smu_write_watermarks_table() */ + +/** + * dm_test_smu_write_watermarks_table_default - Test watermarks table skips non-Navi1x IP versions + * @test: The KUnit test context + */ +static void dm_test_smu_write_watermarks_table_default(struct kunit *test) +{ + struct amdgpu_device *adev = dm_kunit_alloc_adev(test); + + /* + * A zeroed adev reports DCE IP version 0, which is not one of the + * Navi1x versions handled by the switch, so the function returns early. + */ + KUNIT_EXPECT_EQ(test, amdgpu_dm_smu_write_watermarks_table(adev), 0); +} + static struct kunit_case dm_pp_smu_test_cases[] = { /* get_default_clock_levels */ KUNIT_CASE(dm_test_default_clock_levels_display), @@ -2440,6 +2458,8 @@ static struct kunit_case dm_pp_smu_test_cases[] = { KUNIT_CASE(dm_test_nv_get_uclk_dpm_states_ok), KUNIT_CASE(dm_test_nv_get_uclk_dpm_states_unsupported), KUNIT_CASE(dm_test_nv_get_uclk_dpm_states_fail), + /* amdgpu_dm_smu_write_watermarks_table */ + KUNIT_CASE(dm_test_smu_write_watermarks_table_default), {} }; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c index 72d5a4012a3c..49a1d2ae5588 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c @@ -316,21 +316,6 @@ static void dm_test_atomic_destroy_state_no_context(struct kunit *test) dm_atomic_destroy_state(NULL, &dm_state->base); } -/** - * dm_test_smu_write_watermarks_table_default - Test watermarks table skips non-Navi1x IP versions - * @test: The KUnit test context - */ -static void dm_test_smu_write_watermarks_table_default(struct kunit *test) -{ - struct amdgpu_device *adev = dm_kunit_alloc_adev(test); - - /* - * A zeroed adev reports DCE IP version 0, which is not one of the - * Navi1x versions handled by the switch, so the function returns early. - */ - KUNIT_EXPECT_EQ(test, amdgpu_dm_smu_write_watermarks_table(adev), 0); -} - /* Tests for dm_plane_layer_index_cmp() */ /** @@ -1801,7 +1786,6 @@ static struct kunit_case amdgpu_dm_tests[] = { KUNIT_CASE(dm_test_should_update_native_cursor_disable_native), KUNIT_CASE(dm_test_should_update_native_cursor_enable_overlay), KUNIT_CASE(dm_test_atomic_destroy_state_no_context), - KUNIT_CASE(dm_test_smu_write_watermarks_table_default), /* dm_plane_layer_index_cmp */ KUNIT_CASE(dm_test_plane_layer_index_cmp_equal), KUNIT_CASE(dm_test_plane_layer_index_cmp_descending), -- 2.53.0
