From: Justin Chen <[email protected]> [Why & How] need to apply the debug option check for max displayclk.
Reviewed-by: Charlene Liu <[email protected]> Reviewed-by: Dillon Varone <[email protected]> Signed-off-by: Justin Chen <[email protected]> Signed-off-by: Matthew Stewart <[email protected]> Tested-by: Dan Wheeler <[email protected]> --- .../gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c index 4e3d54c92e32..aba7dd65c539 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c @@ -155,6 +155,11 @@ static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_sta context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[0]; } + if (dc->config.forced_clocks || dc->debug.max_disp_clk) { + context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; + context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; + } + /* get global mall allocation */ if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) { context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes); -- 2.53.0
