From: Wayne Lin <[email protected]> [Why] Multi-ROI CRC uses OTG_CRC1_EN for the second engine, but the driver only toggled OTG_CRC_EN and cleared the whole OTG_CRC_CNTL register on disable.
[How] Program engine 1 via OTG_CRC1_EN where supported, disable each engine independently by crc_eng_inst, and add the missing mask on relevant DCN ASICs. Reviewed-by: ChiaHsuan (Tom) Chung <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Signed-off-by: Roman Li <[email protected]> --- .../amd/display/dc/optc/dcn10/dcn10_optc.c | 36 +++++++++++++++---- .../amd/display/dc/optc/dcn10/dcn10_optc.h | 3 +- .../amd/display/dc/optc/dcn31/dcn31_optc.h | 4 +++ .../amd/display/dc/optc/dcn314/dcn314_optc.h | 1 + .../amd/display/dc/optc/dcn32/dcn32_optc.h | 1 + .../amd/display/dc/optc/dcn35/dcn35_optc.c | 26 +++++++++++--- .../amd/display/dc/optc/dcn401/dcn401_optc.h | 1 + .../amd/display/dc/optc/dcn42/dcn42_optc.c | 5 ++- .../amd/display/dc/optc/dcn42/dcn42_optc.h | 2 ++ .../dc/resource/dcn315/dcn315_resource.c | 4 +-- .../dc/resource/dcn316/dcn316_resource.c | 4 +-- 11 files changed, 69 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c index cf8e22289d6a..844705a0e32d 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c @@ -1471,8 +1471,21 @@ bool optc1_configure_crc(struct timing_generator *optc, if (!optc1_is_tg_enabled(optc)) return false; - if (!params->enable || params->reset) - REG_WRITE(OTG_CRC_CNTL, 0); + if (!params->enable || params->reset) { + switch (params->crc_eng_inst) { + case 0: + REG_UPDATE(OTG_CRC_CNTL, OTG_CRC_EN, 0); + break; + case 1: + if (optc1->tg_mask->OTG_CRC1_EN != 0) + REG_UPDATE(OTG_CRC_CNTL, OTG_CRC1_EN, 0); + else + REG_UPDATE(OTG_CRC_CNTL, OTG_CRC_EN, 0); + break; + default: + return false; + } + } if (!params->enable) return true; @@ -1528,10 +1541,16 @@ bool optc1_configure_crc(struct timing_generator *optc, OTG_CRC1_WINDOWB_Y_END, params->windowb_y_end); /* Set crc mode and selection, and enable.*/ - REG_UPDATE_3(OTG_CRC_CNTL, - OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, - OTG_CRC1_SELECT, params->selection, - OTG_CRC_EN, 1); + if (optc1->tg_mask->OTG_CRC1_EN != 0) + REG_UPDATE_3(OTG_CRC_CNTL, + OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, + OTG_CRC1_SELECT, params->selection, + OTG_CRC1_EN, 1); + else + REG_UPDATE_3(OTG_CRC_CNTL, + OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, + OTG_CRC1_SELECT, params->selection, + OTG_CRC_EN, 1); break; default: return false; @@ -1562,7 +1581,10 @@ bool optc1_get_crc(struct timing_generator *optc, uint8_t idx, uint32_t field = 0; struct optc *optc1 = DCN10TG_FROM_TG(optc); - REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); + if (idx == 1 && optc1->tg_mask->OTG_CRC1_EN != 0) + REG_GET(OTG_CRC_CNTL, OTG_CRC1_EN, &field); + else + REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); /* Early return if CRC is not enabled for this CRTC */ if (!field) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h index bceefb5320eb..d099e05c7207 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h @@ -655,7 +655,8 @@ struct dcn_optc_registers { type OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST; #define TG_REG_FIELD_LIST_DCN3_2(type) \ - type OTG_H_TIMING_DIV_MODE_MANUAL; + type OTG_H_TIMING_DIV_MODE_MANUAL;\ + type OTG_CRC1_EN; #define TG_REG_FIELD_LIST_DCN3_5(type) \ type OTG_CRC0_WINDOWA_X_START_READBACK;\ diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h index 98f7d2e299c5..119a954fe3e5 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h @@ -263,6 +263,10 @@ SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\ SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh) +#define OPTC_COMMON_MASK_SH_LIST_DCN31X(mask_sh)\ + OPTC_COMMON_MASK_SH_LIST_DCN3_1(mask_sh),\ + SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh) + void dcn31_timing_generator_init(struct optc *optc1); bool optc31_immediate_disable_crtc(struct timing_generator *optc); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h index 6bfdee3fcf5f..7b43c3ecd46b 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h @@ -205,6 +205,7 @@ SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\ SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\ SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\ SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\ SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h index 7df1ed1102d6..60c01ec28b65 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h @@ -134,6 +134,7 @@ SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_SELECT, mask_sh),\ SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\ SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\ SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\ SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c index 9b7f9d5bbfb3..897f857db448 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c @@ -205,7 +205,10 @@ static bool optc35_get_crc(struct timing_generator *optc, uint8_t idx, uint32_t field = 0; struct optc *optc1 = DCN10TG_FROM_TG(optc); - REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); + if (idx == 1 && optc1->tg_mask->OTG_CRC1_EN != 0) + REG_GET(OTG_CRC_CNTL, OTG_CRC1_EN, &field); + else + REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); /* Early return if CRC is not enabled for this CRTC */ if (!field) @@ -275,8 +278,21 @@ bool optc35_configure_crc(struct timing_generator *optc, if (!optc1_is_tg_enabled(optc)) return false; - if (!params->enable || params->reset) - REG_WRITE(OTG_CRC_CNTL, 0); + if (!params->enable || params->reset) { + switch (params->crc_eng_inst) { + case 0: + REG_UPDATE(OTG_CRC_CNTL, OTG_CRC_EN, 0); + break; + case 1: + if (optc1->tg_mask->OTG_CRC1_EN != 0) + REG_UPDATE(OTG_CRC_CNTL, OTG_CRC1_EN, 0); + else + REG_UPDATE(OTG_CRC_CNTL, OTG_CRC_EN, 0); + break; + default: + return false; + } + } if (!params->enable) return true; @@ -341,13 +357,13 @@ bool optc35_configure_crc(struct timing_generator *optc, REG_UPDATE_4(OTG_CRC_CNTL, OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, OTG_CRC1_SELECT, params->selection, - OTG_CRC_EN, 1, + OTG_CRC1_EN, 1, OTG_CRC_WINDOW_DB_EN, 1); else REG_UPDATE_3(OTG_CRC_CNTL, OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, OTG_CRC1_SELECT, params->selection, - OTG_CRC_EN, 1); + OTG_CRC1_EN, 1); break; default: return false; diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h index fa62737b5b1b..3add972ca2ff 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h @@ -111,6 +111,7 @@ SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\ SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\ SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\ SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\ SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c index 4370d64259e7..fd9c2b6b8b3c 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c @@ -46,7 +46,10 @@ bool optc42_get_crc(struct timing_generator *optc, uint8_t idx, uint32_t field = 0; struct optc *optc1 = DCN10TG_FROM_TG(optc); - REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); + if (idx == 1 && optc1->tg_mask->OTG_CRC1_EN != 0) + REG_GET(OTG_CRC_CNTL, OTG_CRC1_EN, &field); + else + REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); /* Early return if CRC is not enabled for this CRTC */ if (!field) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h index 758cddd9e64f..bc641f6ecd7e 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h @@ -138,6 +138,7 @@ SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\ SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\ SF(OTG0_OTG_CRC0_DATA_R, CRC0_R_CR, mask_sh),\ SF(OTG0_OTG_CRC0_DATA_G, CRC0_G_Y, mask_sh),\ SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ @@ -316,6 +317,7 @@ SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\ SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\ SF(OTG0_OTG_CRC0_DATA_R, CRC0_R_CR, mask_sh),\ SF(OTG0_OTG_CRC0_DATA_G, CRC0_G_Y, mask_sh),\ SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c index 7c78f8ba40ef..470f3bd37314 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c @@ -659,11 +659,11 @@ static const struct dcn_optc_registers optc_regs[] = { }; static const struct dcn_optc_shift optc_shift = { - OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) + OPTC_COMMON_MASK_SH_LIST_DCN31X(__SHIFT) }; static const struct dcn_optc_mask optc_mask = { - OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) + OPTC_COMMON_MASK_SH_LIST_DCN31X(_MASK) }; #define hubp_regs(id)\ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c index b9d2567a4180..d81d241901b4 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c @@ -654,11 +654,11 @@ static const struct dcn_optc_registers optc_regs[] = { }; static const struct dcn_optc_shift optc_shift = { - OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) + OPTC_COMMON_MASK_SH_LIST_DCN31X(__SHIFT) }; static const struct dcn_optc_mask optc_mask = { - OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) + OPTC_COMMON_MASK_SH_LIST_DCN31X(_MASK) }; #define hubp_regs(id)\ -- 2.34.1
