>
> Maybe this is a tangent, but I'm curious about this topology. Is this
> running as a virtualized guest? At the hardware level, a PCIe
> endpoint must have a Root Port somewhere, even if it isn't visible to
> the OS (as is often the case in virtualized guests).
>
Defer to Jon on what the actual hardware configuration is, but this is
physical hardware, no virtualisation, running as the UEFI rather than U-Boot
(devicetree) variant. See:
https://dev.solid-run.com/nxp/lx2160a/com-som/lx2160a
-com-hardware-user-manual#block-diagram
> @@ -2415,13 +2417,24 @@ int pci_do_resource_release_and_resize(struct
> pci_dev *pdev, int resno, int size
> >
> > pci_resize_resource_set_size(pdev, resno, size);
> >
> > - if (!bus->self)
> > - goto out;
> > + if (bus->self) {
>
> I think pci_upstream_bridge() would be better here. Not that this
> device will be a VF (where pci_upstream_bridge() makes a difference),
> but just to be a little more generic.
>
I'll have a look at this and publish a v3 if appropriate.
Liz
---
🐝🍯🐝 Liz Fong-Jones, MACS (Snr) CP, Technical Fellow 🍯🐝🍯
honeycomb.io - The observability platform for teams who manage software
that matters.
lizthegrey.com // linkedin.com/in/efong // bsky.app/profile/lizthegrey.com
