From: YiPeng Chai <[email protected]>

Optimize mp1 dump bank interface.

Signed-off-by: YiPeng Chai <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
---
 drivers/gpu/drm/amd/ras/core/aca.c           | 11 ++---------
 drivers/gpu/drm/amd/ras/core/ras_mp1.c       | 11 +++++++++--
 drivers/gpu/drm/amd/ras/core/ras_mp1.h       |  4 ++--
 drivers/gpu/drm/amd/ras/core/ras_mp1_v13_0.c | 12 ++++++++++--
 4 files changed, 23 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/ras/core/aca.c 
b/drivers/gpu/drm/amd/ras/core/aca.c
index 0b5d55e39e25a..de47137379a16 100644
--- a/drivers/gpu/drm/amd/ras/core/aca.c
+++ b/drivers/gpu/drm/amd/ras/core/aca.c
@@ -284,16 +284,9 @@ static int aca_dump_bank(struct ras_core_context 
*ras_core, u32 ecc_type,
                         int idx, void *data)
 {
        struct aca_bank_reg *bank = (struct aca_bank_reg *)data;
-       int i, ret, reg_cnt;
 
-       reg_cnt = min_t(int, 16, ARRAY_SIZE(bank->regs));
-       for (i = 0; i < reg_cnt; i++) {
-               ret = ras_mp1_dump_bank(ras_core, ecc_type, idx, i, 
&bank->regs[i]);
-               if (ret)
-                       return ret;
-       }
-
-       return 0;
+       return ras_mp1_dump_bank(ras_core, ecc_type, idx,
+                               bank->regs, ARRAY_SIZE(bank->regs));
 }
 
 static uint64_t aca_get_bank_seqno(struct ras_core_context *ras_core,
diff --git a/drivers/gpu/drm/amd/ras/core/ras_mp1.c 
b/drivers/gpu/drm/amd/ras/core/ras_mp1.c
index 26af09f3574a8..97ae049fea496 100644
--- a/drivers/gpu/drm/amd/ras/core/ras_mp1.c
+++ b/drivers/gpu/drm/amd/ras/core/ras_mp1.c
@@ -48,15 +48,22 @@ int ras_mp1_get_bank_count(struct ras_core_context 
*ras_core,
 {
        struct ras_mp1 *mp1 = &ras_core->ras_mp1;
 
+       if (!mp1->ip_func || !mp1->ip_func->get_valid_bank_count)
+               return 0;
+
        return mp1->ip_func->get_valid_bank_count(ras_core, type, count);
 }
 
 int ras_mp1_dump_bank(struct ras_core_context *ras_core,
-               u32 type, u32 idx, u32 reg_idx, u64 *val)
+               u32 type, u32 idx, u64 *regs, u32 regs_sz)
 {
        struct ras_mp1 *mp1 = &ras_core->ras_mp1;
 
-       return mp1->ip_func->dump_valid_bank(ras_core, type, idx, reg_idx, val);
+       if (!mp1->ip_func || !mp1->ip_func->dump_valid_bank)
+               return 0;
+
+       return mp1->ip_func->dump_valid_bank(ras_core,
+                               type, idx, regs, regs_sz);
 }
 
 int ras_mp1_set_debug_mode(struct ras_core_context *ras_core, bool enable)
diff --git a/drivers/gpu/drm/amd/ras/core/ras_mp1.h 
b/drivers/gpu/drm/amd/ras/core/ras_mp1.h
index 5bc7c1b7fdab6..17499e1c9c54b 100644
--- a/drivers/gpu/drm/amd/ras/core/ras_mp1.h
+++ b/drivers/gpu/drm/amd/ras/core/ras_mp1.h
@@ -30,7 +30,7 @@ struct ras_mp1_ip_func {
        int (*get_valid_bank_count)(struct ras_core_context *ras_core,
                        enum ras_err_type type, u32 *count);
        int (*dump_valid_bank)(struct ras_core_context *ras_core,
-               enum ras_err_type type, u32 idx, u32 reg_idx, u64 *val);
+               enum ras_err_type type, u32 idx, u64 *regs, u32 regs_sz);
        int (*set_debug_mode)(struct ras_core_context *ras_core, bool enable);
 };
 
@@ -47,7 +47,7 @@ int ras_mp1_get_bank_count(struct ras_core_context *ras_core,
                            enum ras_err_type type, u32 *count);
 
 int ras_mp1_dump_bank(struct ras_core_context *ras_core,
-               u32 ecc_type, u32 idx, u32 reg_idx, u64 *val);
+               u32 ecc_type, u32 idx, u64 *regs, u32 regs_sz);
 
 int ras_mp1_set_debug_mode(struct ras_core_context *ras_core, bool enable);
 #endif
diff --git a/drivers/gpu/drm/amd/ras/core/ras_mp1_v13_0.c 
b/drivers/gpu/drm/amd/ras/core/ras_mp1_v13_0.c
index b9db91859e5dc..6fd746fe64c48 100644
--- a/drivers/gpu/drm/amd/ras/core/ras_mp1_v13_0.c
+++ b/drivers/gpu/drm/amd/ras/core/ras_mp1_v13_0.c
@@ -75,10 +75,11 @@ static int mp1_v13_0_get_bank_count(struct ras_core_context 
*ras_core,
 }
 
 static int mp1_v13_0_dump_bank(struct ras_core_context *ras_core,
-                       enum ras_err_type type, u32 idx, u32 reg_idx, u64 *val)
+                       enum ras_err_type type, u32 idx, u64 *regs, u32 regs_sz)
 {
        struct ras_mp1 *mp1 = &ras_core->ras_mp1;
        const struct ras_mp1_sys_func *sys_func = mp1->sys_func;
+       int i, ret, reg_cnt;
        u32 msg;
 
        if (!sys_func || !sys_func->mp1_dump_valid_bank)
@@ -96,7 +97,14 @@ static int mp1_v13_0_dump_bank(struct ras_core_context 
*ras_core,
                return -EINVAL;
        }
 
-       return sys_func->mp1_dump_valid_bank(ras_core, msg, idx, reg_idx, val);
+       reg_cnt = min_t(int, 16, regs_sz);
+       for (i = 0; i < reg_cnt; i++) {
+               ret = sys_func->mp1_dump_valid_bank(ras_core, msg, idx, i, 
&regs[i]);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
 }
 
 static int mp1_v13_0_set_debug_mode(struct ras_core_context *ras_core, bool 
enable)
-- 
2.55.0

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