From: YiPeng Chai <[email protected]> Add interface to query nps mode and vram type.
Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/ras/core/core.c | 40 ++++++++++++++++--- drivers/gpu/drm/amd/ras/core/ras.h | 4 +- drivers/gpu/drm/amd/ras/core/ras_psp.c | 18 +++++++-- drivers/gpu/drm/amd/ras/core/ras_umc.c | 19 +-------- drivers/gpu/drm/amd/ras/core/ras_umc.h | 2 - drivers/gpu/drm/amd/ras/core/ras_umc_v12_0.c | 2 +- .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c | 9 ----- .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c | 16 ++++++++ 8 files changed, 69 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/core/core.c b/drivers/gpu/drm/amd/ras/core/core.c index 079032433a916..0815dea06f384 100644 --- a/drivers/gpu/drm/amd/ras/core/core.c +++ b/drivers/gpu/drm/amd/ras/core/core.c @@ -519,14 +519,42 @@ int ras_core_handle_fatal_error(struct ras_core_context *ras_core) uint32_t ras_core_get_curr_nps_mode(struct ras_core_context *ras_core) { - if (!ras_core) - return 0; + int ret; + + if (!ras_core->sys_fn || !ras_core->sys_fn->get_nps_mode) { + RAS_DEV_ERR(ras_core->dev, "Cannot get memory nps mode!\n"); + return UMC_MEMORY_PARTITION_MODE_UNKNOWN; + } - if (ras_core->ras_nbio.ip_func && - ras_core->ras_nbio.ip_func->get_memory_partition_mode) - return ras_core->ras_nbio.ip_func->get_memory_partition_mode(ras_core); + ret = ras_core->sys_fn->get_nps_mode(ras_core); + if (ret < 0) { + RAS_DEV_ERR(ras_core->dev, "Failed to get memory nps mode!\n"); + return UMC_MEMORY_PARTITION_MODE_UNKNOWN; + } else if (!ret) { + RAS_DEV_WARN(ras_core->dev, "None nps mode!\n"); + } + + return ret; +} - return UMC_MEMORY_PARTITION_MODE_UNKNOWN; +uint32_t ras_core_get_vram_type(struct ras_core_context *ras_core) +{ + int ret; + + if (!ras_core->sys_fn || !ras_core->sys_fn->get_vram_type) { + RAS_DEV_ERR(ras_core->dev, "Cannot get vram type!\n"); + return UMC_VRAM_TYPE_UNKNOWN; + } + + ret = ras_core->sys_fn->get_vram_type(ras_core); + if (ret < 0) { + RAS_DEV_ERR(ras_core->dev, "Failed to get vram type!\n"); + return UMC_VRAM_TYPE_UNKNOWN; + } else if (!ret) { + RAS_DEV_WARN(ras_core->dev, "None vram type!\n"); + } + + return ret; } int ras_core_update_ecc_info(struct ras_core_context *ras_core) diff --git a/drivers/gpu/drm/amd/ras/core/ras.h b/drivers/gpu/drm/amd/ras/core/ras.h index e28d51b1992ef..47cc934520448 100644 --- a/drivers/gpu/drm/amd/ras/core/ras.h +++ b/drivers/gpu/drm/amd/ras/core/ras.h @@ -269,6 +269,8 @@ struct ras_sys_func { int (*put_gpu_mem)(struct ras_core_context *ras_core, enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem); int (*check_address_sanity)(struct ras_core_context *ras_core, uint64_t addr); + int (*get_nps_mode)(struct ras_core_context *ras_core); + int (*get_vram_type)(struct ras_core_context *ras_core); }; struct ras_ecc_count { @@ -314,7 +316,6 @@ struct ras_psp_config { }; struct ras_umc_config { - uint32_t umc_vram_type; uint32_t num_umc; }; @@ -417,6 +418,7 @@ bool ras_core_handle_nbio_irq(struct ras_core_context *ras_core, void *data); int ras_core_handle_fatal_error(struct ras_core_context *ras_core); uint32_t ras_core_get_curr_nps_mode(struct ras_core_context *ras_core); +uint32_t ras_core_get_vram_type(struct ras_core_context *ras_core); const char *ras_core_get_ras_block_name(enum ras_block_id block_id); int ras_core_convert_timestamp_to_time(struct ras_core_context *ras_core, uint64_t timestamp, struct ras_time *tm); diff --git a/drivers/gpu/drm/amd/ras/core/ras_psp.c b/drivers/gpu/drm/amd/ras/core/ras_psp.c index 4835228993181..30d22c51758a3 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_psp.c +++ b/drivers/gpu/drm/amd/ras/core/ras_psp.c @@ -81,12 +81,22 @@ static int ras_psp_get_ras_ta_init_param(struct ras_core_context *ras_core, struct ras_ta_init_param *ras_ta_param) { struct ras_psp *psp = &ras_core->ras_psp; + int ret; - if (psp->sys_func && psp->sys_func->get_ras_ta_init_param) - return psp->sys_func->get_ras_ta_init_param(ras_core, ras_ta_param); + if (!psp->sys_func || !psp->sys_func->get_ras_ta_init_param) { + RAS_DEV_ERR(ras_core->dev, "Not config get_ras_ta_init_param API!!\n"); + return -EINVAL; + } - RAS_DEV_ERR(ras_core->dev, "Not config get_ras_ta_init_param API!!\n"); - return -EACCES; + ret = psp->sys_func->get_ras_ta_init_param(ras_core, ras_ta_param); + if (ret) + return ret; + + ras_ta_param->nps_mode = ras_core_get_curr_nps_mode(ras_core); + ras_ta_param->vram_type = ras_core_get_vram_type(ras_core); + ras_ta_param->poison_mode_en = ras_core_poison_supported(ras_core) ? 1 : 0; + + return 0; } static struct gpu_mem_block *ras_psp_get_gpu_mem(struct ras_core_context *ras_core, diff --git a/drivers/gpu/drm/amd/ras/core/ras_umc.c b/drivers/gpu/drm/amd/ras/core/ras_umc.c index fcf65dc5f7146..0237a4f737ec3 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_umc.c +++ b/drivers/gpu/drm/amd/ras/core/ras_umc.c @@ -502,7 +502,7 @@ static bool ras_umc_check_retired_record(struct ras_core_context *ras_core, int i, ret; if (from_eeprom) { - nps = ras_umc->umc_err_data.umc_nps_mode; + nps = ras_core_get_curr_nps_mode(ras_core); ret = ras_umc_eeprom_rec2nps_rec(ras_core, record, nps); if (ret) RAS_DEV_WARN_RATELIMITED(ras_core->dev, @@ -838,24 +838,7 @@ int ras_umc_sw_fini(struct ras_core_context *ras_core) int ras_umc_hw_init(struct ras_core_context *ras_core) { struct ras_umc *ras_umc = &ras_core->ras_umc; - uint32_t nps; - - nps = ras_core_get_curr_nps_mode(ras_core); - - if (!nps || (nps >= UMC_MEMORY_PARTITION_MODE_UNKNOWN)) { - RAS_DEV_ERR(ras_core->dev, "Invalid memory NPS mode: %u!\n", nps); - return -ENODATA; - } - - ras_umc->umc_err_data.umc_nps_mode = nps; - - ras_umc->umc_vram_type = ras_core->config->umc_cfg.umc_vram_type; ras_umc->num_umc = ras_core->config->umc_cfg.num_umc; - if (!ras_umc->umc_vram_type) { - RAS_DEV_ERR(ras_core->dev, "Invalid UMC VRAM Type: %u!\n", - ras_umc->umc_vram_type); - return -ENODATA; - } ras_umc->umc_ip_version = ras_core->config->umc_ip_version; ras_umc->ip_func = ras_umc_get_ip_func(ras_core, ras_umc->umc_ip_version); diff --git a/drivers/gpu/drm/amd/ras/core/ras_umc.h b/drivers/gpu/drm/amd/ras/core/ras_umc.h index af76de70ddd1d..1f257eb3e3df6 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_umc.h +++ b/drivers/gpu/drm/amd/ras/core/ras_umc.h @@ -160,13 +160,11 @@ struct eeprom_store_record { struct ras_umc_err_data { struct eeprom_store_record rom_data; struct eeprom_store_record ram_data; - enum umc_memory_partition_mode umc_nps_mode; uint64_t last_retired_pfn; }; struct ras_umc { u32 umc_ip_version; - u32 umc_vram_type; u32 num_umc; const struct ras_umc_ip_func *ip_func; struct radix_tree_root root; diff --git a/drivers/gpu/drm/amd/ras/core/ras_umc_v12_0.c b/drivers/gpu/drm/amd/ras/core/ras_umc_v12_0.c index ac78c404bed41..63f4e0cf9a415 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_umc_v12_0.c +++ b/drivers/gpu/drm/amd/ras/core/ras_umc_v12_0.c @@ -52,7 +52,7 @@ static void __get_nps_pa_flip_bits(struct ras_core_context *ras_core, enum umc_memory_partition_mode nps, struct umc_flip_bits *flip_bits) { - uint32_t vram_type = ras_core->ras_umc.umc_vram_type; + uint32_t vram_type = ras_core_get_vram_type(ras_core); u32 num_umc = ras_core->ras_umc.num_umc; /* default setting */ diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c index 4b9384bc87b38..030edfebd0b78 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c @@ -267,10 +267,6 @@ static int amdgpu_ras_mgr_get_ras_ta_init_param(struct ras_core_context *ras_cor struct ras_ta_init_param *ras_ta_param) { struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; - uint32_t nps_mode; - - if (ras_core_poison_supported(ras_core)) - ras_ta_param->poison_mode_en = 1; if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) ras_ta_param->dgpu_mode = 1; @@ -279,12 +275,8 @@ static int amdgpu_ras_mgr_get_ras_ta_init_param(struct ras_core_context *ras_cor ras_ta_param->channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; ras_ta_param->active_umc_mask = lower_32_bits(adev->umc.active_mask); - ras_ta_param->vram_type = (uint8_t)adev->gmc.vram_type; ras_ta_param->ext_umc_mask = upper_32_bits(adev->umc.active_mask); - if (!amdgpu_ras_mgr_get_curr_nps_mode(adev, &nps_mode)) - ras_ta_param->nps_mode = nps_mode; - return 0; } @@ -308,7 +300,6 @@ static int amdgpu_ras_mgr_init_umc_config(struct amdgpu_device *adev, { struct ras_umc_config *umc_cfg = &config->umc_cfg; - umc_cfg->umc_vram_type = adev->gmc.vram_type; umc_cfg->num_umc = adev->gmc.num_umc; return 0; diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c index c34af5c8e65ad..17703ed0c7f6d 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c @@ -292,6 +292,20 @@ static int amdgpu_ras_sys_check_address_sanity(struct ras_core_context *ras_core return 0; } +static int amdgpu_ras_sys_get_nps_mode(struct ras_core_context *ras_core) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + + return amdgpu_gmc_query_memory_partition(adev); +} + +static int amdgpu_ras_sys_get_vram_type(struct ras_core_context *ras_core) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + + return adev->gmc.vram_type; +} + const struct ras_sys_func amdgpu_ras_sys_fn = { .ras_notifier = amdgpu_ras_sys_event_notifier, .get_utc_second_timestamp = amdgpu_ras_sys_get_utc_second_timestamp, @@ -303,4 +317,6 @@ const struct ras_sys_func amdgpu_ras_sys_fn = { .get_gpu_mem = amdgpu_ras_sys_get_gpu_mem, .put_gpu_mem = amdgpu_ras_sys_put_gpu_mem, .check_address_sanity = amdgpu_ras_sys_check_address_sanity, + .get_nps_mode = amdgpu_ras_sys_get_nps_mode, + .get_vram_type = amdgpu_ras_sys_get_vram_type, }; -- 2.55.0
