From: YiPeng Chai <[email protected]> Add ras command to obtain ras capabilities.
Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/ras/core/cmd.c | 29 +++++++++++++++++++++++++++++ drivers/gpu/drm/amd/ras/core/cmd.h | 27 ++++++++++++++++++++++++--- 2 files changed, 53 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/core/cmd.c b/drivers/gpu/drm/amd/ras/core/cmd.c index a0e61826c292a..ecd9da6199831 100644 --- a/drivers/gpu/drm/amd/ras/core/cmd.c +++ b/drivers/gpu/drm/amd/ras/core/cmd.c @@ -413,6 +413,34 @@ static int ras_cmd_inject_error(struct ras_core_context *ras_core, return ret; } +static int ras_cmd_get_ras_cap(struct ras_core_context *ras_core, + struct ras_cmd_ctx *cmd, void *data) +{ + struct ras_cmd_get_ras_cap_rsp *output_data = + (struct ras_cmd_get_ras_cap_rsp *)cmd->output_buff_raw; + + output_data->version = 0; + output_data->poison = ras_core_poison_supported(ras_core); + output_data->flex_mca = ras_psp_flex_mca_enabled(ras_core); + output_data->ras_block_mask = ras_core_get_ras_caps(ras_core); + + output_data->ecc_type = 0; + if (output_data->poison) + output_data->ecc_type |= BIT_ULL(RAS_ECC_TYPE_POISON); + + if (output_data->ras_block_mask & BIT_ULL(RAS_BLOCK_ID__UMC)) + output_data->ecc_type |= BIT_ULL(RAS_ECC_TYPE_MEM); + + if (output_data->ras_block_mask & + (BIT_ULL(RAS_BLOCK_ID__GFX) | BIT_ULL(RAS_BLOCK_ID__SDMA))) + output_data->ecc_type |= BIT_ULL(RAS_ECC_TYPE_SRAM); + + + cmd->output_size = sizeof(struct ras_cmd_get_ras_cap_rsp); + + return 0; +} + static struct ras_cmd_func_map ras_cmd_maps[] = { {RAS_CMD__INJECT_ERROR, ras_cmd_inject_error}, {RAS_CMD__GET_BLOCK_ECC_STATUS, ras_get_block_ecc_info}, @@ -423,6 +451,7 @@ static struct ras_cmd_func_map ras_cmd_maps[] = { {RAS_CMD__GET_CPER_RECORD, ras_cmd_get_cper_records}, {RAS_CMD__GET_BATCH_TRACE_SNAPSHOT, ras_cmd_get_batch_trace_snapshot}, {RAS_CMD__GET_BATCH_TRACE_RECORD, ras_cmd_get_batch_trace_records}, + {RAS_CMD__GET_RAS_CAP, ras_cmd_get_ras_cap}, }; int rascore_handle_cmd(struct ras_core_context *ras_core, diff --git a/drivers/gpu/drm/amd/ras/core/cmd.h b/drivers/gpu/drm/amd/ras/core/cmd.h index 4950d0561b30d..728fbe55d1765 100644 --- a/drivers/gpu/drm/amd/ras/core/cmd.h +++ b/drivers/gpu/drm/amd/ras/core/cmd.h @@ -77,6 +77,7 @@ enum ras_cmd_id { RAS_CMD__SET_CMD_AUTO_UPDATE, RAS_CMD__CHECK_ADDRESS_VALIDITY, RAS_CMD__CONVERT_RETIRED_ADDRESS, + RAS_CMD__GET_RAS_CAP, RAS_CMD__SUPPORTED_MAX = RAS_CMD_ID_COMMON_END, }; @@ -95,6 +96,12 @@ enum ras_cmd_response { RAS_CMD__ERROR_UNSUPPORT, }; +enum ras_ecc_type { + RAS_ECC_TYPE_MEM = 0, + RAS_ECC_TYPE_SRAM, + RAS_ECC_TYPE_POISON, +}; + enum ras_error_type { RAS_TYPE_ERROR__NONE = 0, RAS_TYPE_ERROR__PARITY = 1, @@ -204,12 +211,12 @@ struct ras_cmd_inject_error_rsp { struct ras_cmd_dev_info { uint64_t dev_handle; uint32_t location_id; - uint32_t ecc_enabled; - uint32_t ecc_supported; + uint32_t ecc_type; + uint64_t block_mask_bits; uint32_t vf_num; uint32_t asic_type; uint32_t oam_id; - uint32_t reserved[8]; + uint32_t reserved[7]; }; struct ras_cmd_devices_info_rsp { @@ -469,6 +476,20 @@ struct ras_cmd_blocks_ecc_rsp { struct ras_cmd_block_ecc blocks[MAX_RAS_BLOCK_NUM]; }; +struct ras_cmd_get_ras_cap_req { + struct ras_cmd_dev_handle dev; + uint32_t reserved[4]; +}; + +struct ras_cmd_get_ras_cap_rsp { + uint32_t version; + uint32_t ecc_type; + uint32_t poison; + uint32_t flex_mca; + uint64_t ras_block_mask; + uint32_t reserved[8]; +}; + #pragma pack(pop) int ras_cmd_init(struct ras_core_context *ras_core); -- 2.55.0
