From: YiPeng Chai <[email protected]>

Introduce a toggle to control whether RAS RL and TA firmware are loaded
through the legacy path or the RAS module.

Signed-off-by: YiPeng Chai <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c          | 12 ++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h          |  2 ++
 drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c |  6 +++++-
 3 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index d5998497b22e0..55d293a2ee381 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1175,6 +1175,7 @@ static int psp_boot_config_set(struct amdgpu_device 
*adev, uint32_t boot_cfg)
 
 static int psp_rl_load(struct amdgpu_device *adev)
 {
+       struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
        int ret;
        struct psp_context *psp = &adev->psp;
        struct psp_gfx_cmd_resp *cmd;
@@ -1182,6 +1183,9 @@ static int psp_rl_load(struct amdgpu_device *adev)
        if (!is_psp_fw_valid(psp->rl))
                return 0;
 
+       if (con && con->uniras_load_ras_fw)
+               return 0;
+
        cmd = acquire_psp_cmd_buf(psp);
 
        ret = psp_copy_fw(psp, psp->rl.start_addr, psp->rl.size_bytes);
@@ -2327,9 +2331,13 @@ int psp_ras_invoke(struct psp_context *psp, uint32_t 
ta_cmd_id)
 int psp_ras_enable_features(struct psp_context *psp,
                union ta_ras_cmd_input *info, bool enable)
 {
+       struct amdgpu_ras *con = amdgpu_ras_get_context(psp->adev);
        enum ras_command cmd_id;
        int ret;
 
+       if (con && con->uniras_load_ras_fw)
+               return 0;
+
        if (!psp->ras_context.context.initialized || !info)
                return -EINVAL;
 
@@ -2369,6 +2377,7 @@ int psp_ras_initialize(struct psp_context *psp)
        int ret;
        uint32_t boot_cfg = 0xFF;
        struct amdgpu_device *adev = psp->adev;
+       struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
        struct ta_ras_shared_memory *ras_cmd;
 
        /*
@@ -2436,6 +2445,9 @@ int psp_ras_initialize(struct psp_context *psp)
                }
        }
 
+       if (con && con->uniras_load_ras_fw)
+               return 0;
+
        psp->ras_context.context.mem_context.shared_mem_size = 
PSP_RAS_SHARED_MEM_SIZE;
        psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
index 63ea7d39b84e1..84799c39ef81c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
@@ -572,6 +572,8 @@ struct amdgpu_ras {
 
        /* Disable/Enable uniras switch */
        bool uniras_enabled;
+       bool uniras_load_ras_fw;
+       const struct ras_smu_drv *ras_smu_drv;
 };
 
 struct ras_fs_data {
diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c 
b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
index 3797a17385b44..34b4b3345259a 100644
--- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
+++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
@@ -188,9 +188,10 @@ static int amdgpu_ras_mgr_get_ras_psp_system_status(struct 
ras_core_context *ras
                        struct ras_psp_sys_status *status)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
+       struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 
        status->psp_cmd_mutex = &adev->psp.mutex;
-       status->uniras_load_fw = false;
+       status->uniras_load_fw = con ? con->uniras_load_ras_fw : false;
 
        status->use_dedicated_memory = !status->uniras_load_fw;
 
@@ -310,6 +311,9 @@ int amdgpu_ras_mgr_sw_init(struct amdgpu_device *adev)
        else
                return 0;
 
+       /* Enable uniras to load RL firmware and TA firmware */
+       con->uniras_load_ras_fw = true;
+
        ras_mgr = kzalloc_obj(*ras_mgr);
        if (!ras_mgr)
                return -EINVAL;
-- 
2.55.0

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