From: Lijo Lazar <[email protected]> Control register is access restricted. Use the read-only copy to read the partition settings.
Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 11 ++++------- .../drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h | 2 ++ .../drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h | 4 +++- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 9dd7a33357199..3f757dfcd1c36 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -839,19 +839,16 @@ static void gfx_v12_1_select_me_pipe_q(struct amdgpu_device *adev, soc_v1_0_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); } -#define regGFX_IMU_PARTITION_SWITCH 0x5f8c -#define regGFX_IMU_PARTITION_SWITCH_BASE_IDX 1 -#define GFX_IMU_PARTITION_SWITCH__TOTAL_XCCS_IN_XCP__SHIFT 0x2 -#define GFX_IMU_PARTITION_SWITCH__TOTAL_XCCS_IN_XCP_MASK 0x0000003CL - static int gfx_v12_1_get_xccs_per_xcp(struct amdgpu_device *adev) { u32 reg_data; /* the register data is expected to be the same on all instances */ - reg_data = RREG32_SOC15(GC, GET_INST(GC, 0), regGFX_IMU_PARTITION_SWITCH); + reg_data = RREG32_SOC15(GC, GET_INST(GC, 0), + regGFX_IMU_PARTITION_SWITCH_SHADOW); - return REG_GET_FIELD(reg_data, GFX_IMU_PARTITION_SWITCH, TOTAL_XCCS_IN_XCP); + return REG_GET_FIELD(reg_data, GFX_IMU_PARTITION_SWITCH_SHADOW, + TOTAL_XCCS_IN_XCP); } static int gfx_v12_1_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h index 025e5490e6f12..dbd497d9fac15 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h @@ -7369,6 +7369,8 @@ #define regGFX_IMU_TIMER1_VALUE 0x40d1 #define regGFX_IMU_TIMER1_VALUE_BASE_IDX 1 #define regGFX_IMU_FUSE_CTRL 0x40e0 +#define regGFX_IMU_PARTITION_SWITCH_SHADOW 0x40f8 +#define regGFX_IMU_PARTITION_SWITCH_SHADOW_BASE_IDX 1 #define regGFX_IMU_FUSE_CTRL_BASE_IDX 1 #define regGFX_IMU_D_RAM_ADDR 0x40fc #define regGFX_IMU_D_RAM_ADDR_BASE_IDX 1 diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h index 1cf890de35cbd..68dfafd8d027f 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h @@ -23556,7 +23556,9 @@ //GFX_IMU_I_RAM_DATA #define GFX_IMU_I_RAM_DATA__DATA__SHIFT 0x0 #define GFX_IMU_I_RAM_DATA__DATA_MASK 0xFFFFFFFFL - +//GFX_IMU_PARTITION_SWITCH_SHADOW +#define GFX_IMU_PARTITION_SWITCH_SHADOW__TOTAL_XCCS_IN_XCP__SHIFT 0x2 +#define GFX_IMU_PARTITION_SWITCH_SHADOW__TOTAL_XCCS_IN_XCP_MASK 0x0000003CL // addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_grbmhdec //GRBMH_CNTL -- 2.55.0
