From: Alex Sierra <[email protected]> add_hw_queue, remove_hw_queue, set_hw_resources_1 and inv_tlbs_pasid read master_xcc_ids[MES_PIPE_INST(xcc_id, SCHED)]. That only worked for xcc_id == 0; with a non-zero target (e.g. partition-1 master in DPX) it read an uninitialised slot. Index by xcc_id consistently, and fix the related shared_cmd_buf_gpu_addr[] index in set_hw_resources_1() to use MES_PIPE_INST(master_xcc_id, pipe). All indexing stays in logical XCC space, so this remains correct with harvested XCCs; the existing ip_map / GET_INST() translation handles the logical-to-physical conversion at the HW register boundary.
Signed-off-by: Alex Sierra <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/mes_v12_1.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c index f1098118d5c05..4df3f0204dbbe 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c @@ -291,10 +291,9 @@ static int mes_v12_1_add_hw_queue(struct amdgpu_mes *mes, { union MESAPI__ADD_QUEUE mes_add_queue_pkt; int xcc_id = input->xcc_id; - int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); if (mes->enable_coop_mode) - xcc_id = mes->master_xcc_ids[inst]; + xcc_id = mes->master_xcc_ids[xcc_id]; memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); @@ -352,10 +351,9 @@ static int mes_v12_1_remove_hw_queue(struct amdgpu_mes *mes, { union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; int xcc_id = input->xcc_id; - int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); if (mes->enable_coop_mode) - xcc_id = mes->master_xcc_ids[inst]; + xcc_id = mes->master_xcc_ids[xcc_id]; memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); @@ -663,7 +661,7 @@ static int mes_v12_1_set_hw_resources_1(struct amdgpu_mes *mes, int pipe, int xcc_id) { union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt; - int master_xcc_id, inst = MES_PIPE_INST(xcc_id, pipe); + int master_xcc_id; memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt)); @@ -673,14 +671,14 @@ static int mes_v12_1_set_hw_resources_1(struct amdgpu_mes *mes, mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100; /* From version 0x74 above, pipe1 support use shared command buffer - to distribute some tasks on individual XCCs*/ + to distribute some tasks on individual XCCs*/ if (mes->enable_coop_mode && ((pipe == AMDGPU_MES_SCHED_PIPE) || ((mes->kiq_version & AMDGPU_MES_VERSION_MASK) >= 0x74))) { - master_xcc_id = mes->master_xcc_ids[inst]; + master_xcc_id = mes->master_xcc_ids[xcc_id]; mes_set_hw_res_1_pkt.mes_coop_mode = 1; mes_set_hw_res_1_pkt.coop_sch_shared_mc_addr = - mes->shared_cmd_buf_gpu_addr[master_xcc_id + pipe]; + mes->shared_cmd_buf_gpu_addr[MES_PIPE_INST(master_xcc_id, pipe)]; } return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, @@ -945,11 +943,11 @@ static int mes_v12_1_inv_tlbs_pasid(struct amdgpu_mes *mes, { union MESAPI__INV_TLBS mes_inv_tlbs; int xcc_id = input->xcc_id; - int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); int ret; + /* See mes_v12_1_add_hw_queue() for the indexing rationale. */ if (mes->enable_coop_mode) - xcc_id = mes->master_xcc_ids[inst]; + xcc_id = mes->master_xcc_ids[xcc_id]; memset(&mes_inv_tlbs, 0, sizeof(mes_inv_tlbs)); -- 2.55.0
