From: Hawking Zhang <[email protected]> Initialize amdgpu_gfx_config using values from gc_info_v1_5.
Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 21 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 3 + drivers/gpu/drm/amd/include/discovery.h | 125 ++++++++++++------ 3 files changed, 109 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 836a412fcdc2d..b567860aa555a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1987,6 +1987,7 @@ union gc_info { struct gc_info_v1_1 v1_1; struct gc_info_v1_2 v1_2; struct gc_info_v1_3 v1_3; + struct gc_info_v1_5 v1_5; struct gc_info_v2_0 v2; struct gc_info_v2_1 v2_1; }; @@ -2016,7 +2017,7 @@ static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) case 1: adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + - le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); + le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); @@ -2057,6 +2058,24 @@ static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size); } + if (le16_to_cpu(gc_info->v1.header.version_minor) == 4 || + le16_to_cpu(gc_info->v1.header.version_minor) > 5) { + dev_err(adev->dev, + "Unsupported GC info table %d.%d\n", + le16_to_cpu(gc_info->v1.header.version_major), + le16_to_cpu(gc_info->v1.header.version_minor)); + return -EINVAL; + } + if (le16_to_cpu(gc_info->v1.header.version_minor) == 5) { + adev->gfx.config.gc_max_num_residency_ways = le32_to_cpu(gc_info->v1_5.gc_max_num_residency_ways); + adev->gfx.config.gc_cache_ways_size_in_bytes = le32_to_cpu(gc_info->v1_5.gc_cache_ways_size_in_bytes); + adev->gfx.config.gc_reserved = le32_to_cpu(gc_info->v1_5.gc_reserved); + /* GC info v1.5 derives max_cu_per_sh from the combined SA/SA1 WGP counts. */ + adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + + le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa) + + le32_to_cpu(gc_info->v1_5.gc_num_wgp0_per_sa1) + + le32_to_cpu(gc_info->v1_5.gc_num_wgp1_per_sa1); + } break; case 2: adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 1023719c18bb6..6722213db8f01 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -307,6 +307,9 @@ struct amdgpu_gfx_config { uint32_t gc_scalar_data_cache_size_per_sqc; uint32_t gc_scalar_data_cache_line_size; uint32_t gc_tcc_cache_line_size; + uint32_t gc_max_num_residency_ways; + uint32_t gc_cache_ways_size_in_bytes; + uint32_t gc_reserved; }; struct amdgpu_cu_info { diff --git a/drivers/gpu/drm/amd/include/discovery.h b/drivers/gpu/drm/amd/include/discovery.h index 76c9f951bc1c8..575705653e957 100644 --- a/drivers/gpu/drm/amd/include/discovery.h +++ b/drivers/gpu/drm/amd/include/discovery.h @@ -272,45 +272,92 @@ struct gc_info_v1_2 { }; struct gc_info_v1_3 { - struct gpu_info_header header; - uint32_t gc_num_se; - uint32_t gc_num_wgp0_per_sa; - uint32_t gc_num_wgp1_per_sa; - uint32_t gc_num_rb_per_se; - uint32_t gc_num_gl2c; - uint32_t gc_num_gprs; - uint32_t gc_num_max_gs_thds; - uint32_t gc_gs_table_depth; - uint32_t gc_gsprim_buff_depth; - uint32_t gc_parameter_cache_depth; - uint32_t gc_double_offchip_lds_buffer; - uint32_t gc_wave_size; - uint32_t gc_max_waves_per_simd; - uint32_t gc_max_scratch_slots_per_cu; - uint32_t gc_lds_size; - uint32_t gc_num_sc_per_se; - uint32_t gc_num_sa_per_se; - uint32_t gc_num_packer_per_sc; - uint32_t gc_num_gl2a; - uint32_t gc_num_tcp_per_sa; - uint32_t gc_num_sdp_interface; - uint32_t gc_num_tcps; - uint32_t gc_num_tcp_per_wpg; - uint32_t gc_tcp_l1_size; - uint32_t gc_num_sqc_per_wgp; - uint32_t gc_l1_instruction_cache_size_per_sqc; - uint32_t gc_l1_data_cache_size_per_sqc; - uint32_t gc_gl1c_per_sa; - uint32_t gc_gl1c_size_per_instance; - uint32_t gc_gl2c_per_gpu; - uint32_t gc_tcp_size_per_cu; - uint32_t gc_tcp_cache_line_size; - uint32_t gc_instruction_cache_size_per_sqc; - uint32_t gc_instruction_cache_line_size; - uint32_t gc_scalar_data_cache_size_per_sqc; - uint32_t gc_scalar_data_cache_line_size; - uint32_t gc_tcc_size; - uint32_t gc_tcc_cache_line_size; + struct gpu_info_header header; + uint32_t gc_num_se; + uint32_t gc_num_wgp0_per_sa; + uint32_t gc_num_wgp1_per_sa; + uint32_t gc_num_rb_per_se; + uint32_t gc_num_gl2c; + uint32_t gc_num_gprs; + uint32_t gc_num_max_gs_thds; + uint32_t gc_gs_table_depth; + uint32_t gc_gsprim_buff_depth; + uint32_t gc_parameter_cache_depth; + uint32_t gc_double_offchip_lds_buffer; + uint32_t gc_wave_size; + uint32_t gc_max_waves_per_simd; + uint32_t gc_max_scratch_slots_per_cu; + uint32_t gc_lds_size; + uint32_t gc_num_sc_per_se; + uint32_t gc_num_sa_per_se; + uint32_t gc_num_packer_per_sc; + uint32_t gc_num_gl2a; + uint32_t gc_num_tcp_per_sa; + uint32_t gc_num_sdp_interface; + uint32_t gc_num_tcps; + uint32_t gc_num_tcp_per_wpg; + uint32_t gc_tcp_l1_size; + uint32_t gc_num_sqc_per_wgp; + uint32_t gc_l1_instruction_cache_size_per_sqc; + uint32_t gc_l1_data_cache_size_per_sqc; + uint32_t gc_gl1c_per_sa; + uint32_t gc_gl1c_size_per_instance; + uint32_t gc_gl2c_per_gpu; + uint32_t gc_tcp_size_per_cu; + uint32_t gc_tcp_cache_line_size; + uint32_t gc_instruction_cache_size_per_sqc; + uint32_t gc_instruction_cache_line_size; + uint32_t gc_scalar_data_cache_size_per_sqc; + uint32_t gc_scalar_data_cache_line_size; + uint32_t gc_tcc_size; + uint32_t gc_tcc_cache_line_size; +}; + +struct gc_info_v1_5 { + struct gpu_info_header header; + uint32_t gc_num_se; + uint32_t gc_num_wgp0_per_sa; + uint32_t gc_num_wgp1_per_sa; + uint32_t gc_num_rb_per_se; + uint32_t gc_num_gl2c; + uint32_t gc_num_gprs; + uint32_t gc_num_max_gs_thds; + uint32_t gc_gs_table_depth; + uint32_t gc_gsprim_buff_depth; + uint32_t gc_parameter_cache_depth; + uint32_t gc_double_offchip_lds_buffer; + uint32_t gc_wave_size; + uint32_t gc_max_waves_per_simd; + uint32_t gc_max_scratch_slots_per_cu; + uint32_t gc_lds_size; + uint32_t gc_num_sc_per_se; + uint32_t gc_num_sa_per_se; + uint32_t gc_num_packer_per_sc; + uint32_t gc_num_gl2a; + uint32_t gc_num_tcp_per_sa; + uint32_t gc_num_sdp_interface; + uint32_t gc_num_tcps; + uint32_t gc_num_tcp_per_wpg; + uint32_t gc_tcp_l1_size; + uint32_t gc_num_sqc_per_wgp; + uint32_t gc_l1_instruction_cache_size_per_sqc; + uint32_t gc_l1_data_cache_size_per_sqc; + uint32_t gc_gl1c_per_sa; + uint32_t gc_gl1c_size_per_instance; + uint32_t gc_gl2c_per_gpu; + uint32_t gc_tcp_size_per_cu; + uint32_t gc_tcp_cache_line_size; + uint32_t gc_instruction_cache_size_per_sqc; + uint32_t gc_instruction_cache_line_size; + uint32_t gc_scalar_data_cache_size_per_sqc; + uint32_t gc_scalar_data_cache_line_size; + uint32_t gc_tcc_size; + uint32_t gc_tcc_cache_line_size; + uint32_t gc_num_wgp0_per_sa1; + uint32_t gc_num_wgp1_per_sa1; + uint32_t gc_max_num_residency_ways; + uint32_t gc_cache_ways_size_in_bytes; + uint32_t gc_reserved; }; struct gc_info_v2_0 { -- 2.55.0
