gmc9-12 use the same logic for almost all of these, so move it to helpers and remove the gmc specific functions.
Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 195 +++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 7 + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 + drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 199 +-------------------- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 204 +--------------------- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 219 +----------------------- drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c | 195 +-------------------- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 92 +--------- 8 files changed, 221 insertions(+), 892 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 2800eebe50649..185290a392bec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -951,6 +951,201 @@ static int amdgpu_gmc_flush_gpu_tlb_mes_helper(struct amdgpu_device *adev, return 0; } +/** + * amdgpu_gmc_flush_gpu_tlb_pasid_helper - tlb flush via pasid + * + * @adev: amdgpu_device pointer + * @pasid: pasid to be flush + * @flush_type: the flush type + * @all_hub: flush all hubs + * @inst: is used to select which instance of KIQ to use for the invalidation + * + * A helper to flush the TLB for the requested pasid using other callbacks. + */ +void amdgpu_gmc_flush_gpu_tlb_pasid_helper(struct amdgpu_device *adev, + uint16_t pasid, uint32_t flush_type, + bool all_hub, uint32_t inst) +{ + uint16_t queried; + int vmid, i; + + for (vmid = 1; vmid < 16; vmid++) { + bool valid; + + valid = adev->gmc.gmc_funcs->get_vmid_pasid_mapping_info(adev, vmid, inst, + &queried); + if (!valid || queried != pasid) + continue; + + if (all_hub) { + for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) + adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid, i, + flush_type); + } else { + adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(inst), + flush_type); + } + } +} + +/** + * amdgpu_gmc_flush_gpu_tlb_helper - gart tlb flush callback + * + * @adev: amdgpu_device pointer + * @vmid: vm instance to flush + * @vmhub: which hub to flush + * @flush_type: the flush type + * + * Flush the TLB for the requested page table. + */ +void amdgpu_gmc_flush_gpu_tlb_helper(struct amdgpu_device *adev, uint32_t vmid, + uint32_t vmhub, uint32_t flush_type) +{ + bool use_semaphore = adev->gmc.gmc_funcs->use_invalidate_semaphore(adev, vmhub); + struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; + u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); + /* Use register 17 for GART */ + const unsigned int eng = 17; + unsigned char hub_ip; + u32 sem, req, ack; + unsigned int i; + u32 tmp, inst; + + if (AMDGPU_IS_GFXHUB(vmhub) && !adev->gfx.is_poweron) + return; + + sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; + req = hub->vm_inv_eng0_req + hub->eng_distance * eng; + ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; + + + if (vmhub >= AMDGPU_MMHUB0(0)) + inst = 0; + else + inst = vmhub; + + /* flush hdp cache */ + amdgpu_device_flush_hdp(adev, NULL); + + /* This is necessary for SRIOV as well as for GFXOFF to function + * properly under bare metal + */ + if ((adev->gfx.kiq[inst].ring.sched.ready || + adev->mes.ring[MES_PIPE_INST(inst, 0)].sched.ready) && + !adev->gmc.use_mmio_for_tlb_flush) { + amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, + 1 << vmid, inst); + return; + } + + /* This path is needed before KIQ/MES/GFXOFF are set up */ + hub_ip = AMDGPU_IS_GFXHUB(vmhub) ? GC_HWIP : MMHUB_HWIP; + + /* disabllow gfxoff when we invalidate */ + if (hub_ip == GC_HWIP) + amdgpu_gfx_off_ctrl(adev, false); + + spin_lock(&adev->gmc.invalidate_lock); + /* + * It may lose gpuvm invalidate acknowldege state across power-gating + * off cycle, add semaphore acquire before invalidation and semaphore + * release after invalidation to avoid entering power gated state + * to WA the Issue + */ + + /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ + if (use_semaphore) { + for (i = 0; i < adev->usec_timeout; i++) { + /* a read return value of 1 means semaphore acuqire */ + tmp = RREG32_RLC_NO_KIQ(sem, hub_ip); + if (tmp & 0x1) + break; + udelay(1); + } + + if (i >= adev->usec_timeout) + DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); + } + + WREG32_RLC_NO_KIQ(req, inv_req, hub_ip); + + /* Wait for ACK with a delay.*/ + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32_RLC_NO_KIQ(ack, hub_ip); + tmp &= 1 << vmid; + if (tmp) + break; + + udelay(1); + } + + /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ + if (use_semaphore) + WREG32_RLC_NO_KIQ(sem, 0, hub_ip); + + /* Issue additional private vm invalidation to MMHUB */ + if ((vmhub != AMDGPU_GFXHUB(0)) && + (hub->vm_l2_bank_select_reserved_cid2) && + !amdgpu_sriov_vf(adev)) { + inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); + /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ + inv_req |= (1 << 25); + /* Issue private invalidation */ + WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); + /* Read back to ensure invalidation is done*/ + RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); + } + + spin_unlock(&adev->gmc.invalidate_lock); + + if (hub_ip == GC_HWIP) + amdgpu_gfx_off_ctrl(adev, true); + + if (i >= adev->usec_timeout) + dev_err(adev->dev, "Timeout waiting for VM flush ACK!\n"); +} + +uint64_t amdgpu_gmc_emit_flush_gpu_tlb_helper(struct amdgpu_ring *ring, + unsigned vmid, uint64_t pd_addr) +{ + bool use_semaphore = + ring->adev->gmc.gmc_funcs->use_invalidate_semaphore(ring->adev, + ring->vm_hub); + struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; + uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); + unsigned eng = ring->vm_inv_eng; + + if (use_semaphore) + /* a read return value of 1 means semaphore acuqire */ + amdgpu_ring_emit_reg_wait(ring, + hub->vm_inv_eng0_sem + + hub->eng_distance * eng, 0x1, 0x1); + + amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + + (hub->ctx_addr_distance * vmid), + lower_32_bits(pd_addr)); + + amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + + (hub->ctx_addr_distance * vmid), + upper_32_bits(pd_addr)); + + amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + + hub->eng_distance * eng, + hub->vm_inv_eng0_ack + + hub->eng_distance * eng, + req, 1 << vmid); + + if (use_semaphore) + /* + * add semaphore release after invalidation, + * write with 0 means semaphore release + */ + amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + + hub->eng_distance * eng, 0); + + return pd_addr; +} + int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, uint32_t flush_type, bool all_hub, uint32_t inst) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index f20f08630408e..22814dd451430 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -459,6 +459,13 @@ int amdgpu_gmc_handle_retry_fault(struct amdgpu_device *adev, bool write_fault); int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev); int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev); +void amdgpu_gmc_flush_gpu_tlb_pasid_helper(struct amdgpu_device *adev, + uint16_t pasid, uint32_t flush_type, + bool all_hub, uint32_t inst); +void amdgpu_gmc_flush_gpu_tlb_helper(struct amdgpu_device *adev, uint32_t vmid, + uint32_t vmhub, uint32_t flush_type); +uint64_t amdgpu_gmc_emit_flush_gpu_tlb_helper(struct amdgpu_ring *ring, + unsigned vmid, uint64_t pd_addr); void amdgpu_gmc_flush_gpu_tlb_gart(struct amdgpu_device *adev, uint32_t vmhub); int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 5033f85d31022..654bf7f780d59 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7497,6 +7497,8 @@ static int gfx_v10_0_hw_init(struct amdgpu_ip_block *ip_block) int r; struct amdgpu_device *adev = ip_block->adev; + adev->gfx.is_poweron = true; + if (!amdgpu_emu_mode) gfx_v10_0_init_golden_registers(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index e716a86ba2913..35397b44c9dfc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -223,195 +223,6 @@ static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( * by the amdgpu vm/hsa code. */ -/** - * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback - * - * @adev: amdgpu_device pointer - * @vmid: vm instance to flush - * @vmhub: vmhub type - * @flush_type: the flush type - * - * Flush the TLB for the requested page table. - */ -static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, - uint32_t vmhub, uint32_t flush_type) -{ - bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); - struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; - u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); - /* Use register 17 for GART */ - const unsigned int eng = 17; - unsigned char hub_ip = 0; - u32 sem, req, ack; - unsigned int i; - u32 tmp; - - sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; - req = hub->vm_inv_eng0_req + hub->eng_distance * eng; - ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; - - /* flush hdp cache */ - amdgpu_device_flush_hdp(adev, NULL); - - /* This is necessary for SRIOV as well as for GFXOFF to function - * properly under bare metal - */ - if (adev->gfx.kiq[0].ring.sched.ready && !adev->enable_mes && - !adev->gmc.use_mmio_for_tlb_flush) { - amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, - 1 << vmid, GET_INST(GC, 0)); - return; - } - - /* This path is needed before KIQ/MES/GFXOFF are set up */ - hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; - - /* disabllow gfxoff when we invalidate */ - if (hub_ip == GC_HWIP) - amdgpu_gfx_off_ctrl(adev, false); - - spin_lock(&adev->gmc.invalidate_lock); - /* - * It may lose gpuvm invalidate acknowldege state across power-gating - * off cycle, add semaphore acquire before invalidation and semaphore - * release after invalidation to avoid entering power gated state - * to WA the Issue - */ - - /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ - if (use_semaphore) { - for (i = 0; i < adev->usec_timeout; i++) { - /* a read return value of 1 means semaphore acuqire */ - tmp = RREG32_RLC_NO_KIQ(sem, hub_ip); - if (tmp & 0x1) - break; - udelay(1); - } - - if (i >= adev->usec_timeout) - DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); - } - - WREG32_RLC_NO_KIQ(req, inv_req, hub_ip); - - /* - * Issue a dummy read to wait for the ACK register to be cleared - * to avoid a false ACK due to the new fast GRBM interface. - */ - if ((vmhub == AMDGPU_GFXHUB(0)) && - (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 3, 0))) - RREG32_RLC_NO_KIQ(req, hub_ip); - - /* Wait for ACK with a delay.*/ - for (i = 0; i < adev->usec_timeout; i++) { - tmp = RREG32_RLC_NO_KIQ(ack, hub_ip); - tmp &= 1 << vmid; - if (tmp) - break; - - udelay(1); - } - - /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ - if (use_semaphore) - WREG32_RLC_NO_KIQ(sem, 0, hub_ip); - - spin_unlock(&adev->gmc.invalidate_lock); - - if (hub_ip == GC_HWIP) - amdgpu_gfx_off_ctrl(adev, true); - - if (i >= adev->usec_timeout) - dev_err(adev->dev, "Timeout waiting for VM flush hub: %d!\n", - vmhub); -} - -/** - * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid - * - * @adev: amdgpu_device pointer - * @pasid: pasid to be flush - * @flush_type: the flush type - * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB() - * @inst: is used to select which instance of KIQ to use for the invalidation - * - * Flush the TLB for the requested pasid. - */ -static void gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, - uint16_t pasid, uint32_t flush_type, - bool all_hub, uint32_t inst) -{ - uint16_t queried; - int vmid, i; - - for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { - bool valid; - - valid = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 0, - &queried); - if (!valid || queried != pasid) - continue; - - if (all_hub) { - for_each_set_bit(i, adev->vmhubs_mask, - AMDGPU_MAX_VMHUBS) - gmc_v10_0_flush_gpu_tlb(adev, vmid, i, - flush_type); - } else { - gmc_v10_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), - flush_type); - } - } -} - -static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, - unsigned int vmid, uint64_t pd_addr) -{ - bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); - struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; - uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); - unsigned int eng = ring->vm_inv_eng; - - /* - * It may lose gpuvm invalidate acknowldege state across power-gating - * off cycle, add semaphore acquire before invalidation and semaphore - * release after invalidation to avoid entering power gated state - * to WA the Issue - */ - - /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ - if (use_semaphore) - /* a read return value of 1 means semaphore acuqire */ - amdgpu_ring_emit_reg_wait(ring, - hub->vm_inv_eng0_sem + - hub->eng_distance * eng, 0x1, 0x1); - - amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + - (hub->ctx_addr_distance * vmid), - lower_32_bits(pd_addr)); - - amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + - (hub->ctx_addr_distance * vmid), - upper_32_bits(pd_addr)); - - amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + - hub->eng_distance * eng, - hub->vm_inv_eng0_ack + - hub->eng_distance * eng, - req, 1 << vmid); - - /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ - if (use_semaphore) - /* - * add semaphore release after invalidation, - * write with 0 means semaphore release - */ - amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + - hub->eng_distance * eng, 0); - - return pd_addr; -} - static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, unsigned int pasid) { @@ -552,9 +363,9 @@ static unsigned int gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) } static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { - .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, - .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, - .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, + .flush_gpu_tlb = amdgpu_gmc_flush_gpu_tlb_helper, + .flush_gpu_tlb_pasid = amdgpu_gmc_flush_gpu_tlb_pasid_helper, + .emit_flush_gpu_tlb = amdgpu_gmc_emit_flush_gpu_tlb_helper, .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, .get_vmid_pasid_mapping_info = gmc_v10_0_get_atc_vmid_pasid_mapping_info, .use_invalidate_semaphore = gmc_v10_0_use_invalidate_semaphore, @@ -957,9 +768,9 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) if (!adev->in_s0ix) adev->gfxhub.funcs->set_fault_enable_default(adev, value); adev->mmhub.funcs->set_fault_enable_default(adev, value); - gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); + adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); if (!adev->in_s0ix) - gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); + adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); drm_info(adev_to_drm(adev), "PCIE GART of %uM enabled (table at 0x%016llX).\n", (unsigned int)(adev->gmc.gart_size >> 20), diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 8b95a1281886b..b05dda4b0b690 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -208,202 +208,6 @@ static bool gmc_v11_0_get_vmid_pasid_mapping_info( return !!(*p_pasid); } -/** - * gmc_v11_0_flush_gpu_tlb - gart tlb flush callback - * - * @adev: amdgpu_device pointer - * @vmid: vm instance to flush - * @vmhub: which hub to flush - * @flush_type: the flush type - * - * Flush the TLB for the requested page table. - */ -static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, - uint32_t vmhub, uint32_t flush_type) -{ - bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(adev, vmhub); - struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; - u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); - /* Use register 17 for GART */ - const unsigned int eng = 17; - unsigned char hub_ip; - u32 sem, req, ack; - unsigned int i; - u32 tmp; - - if ((vmhub == AMDGPU_GFXHUB(0)) && !adev->gfx.is_poweron) - return; - - sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; - req = hub->vm_inv_eng0_req + hub->eng_distance * eng; - ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; - - /* flush hdp cache */ - amdgpu_device_flush_hdp(adev, NULL); - - /* This is necessary for SRIOV as well as for GFXOFF to function - * properly under bare metal - */ - if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring[0].sched.ready) && - !adev->gmc.use_mmio_for_tlb_flush) { - amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, - 1 << vmid, GET_INST(GC, 0)); - return; - } - - /* This path is needed before KIQ/MES/GFXOFF are set up */ - hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; - - /* disabllow gfxoff when we invalidate */ - if (hub_ip == GC_HWIP) - amdgpu_gfx_off_ctrl(adev, false); - - spin_lock(&adev->gmc.invalidate_lock); - /* - * It may lose gpuvm invalidate acknowldege state across power-gating - * off cycle, add semaphore acquire before invalidation and semaphore - * release after invalidation to avoid entering power gated state - * to WA the Issue - */ - - /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ - if (use_semaphore) { - for (i = 0; i < adev->usec_timeout; i++) { - /* a read return value of 1 means semaphore acuqire */ - tmp = RREG32_RLC_NO_KIQ(sem, hub_ip); - if (tmp & 0x1) - break; - udelay(1); - } - - if (i >= adev->usec_timeout) - DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); - } - - WREG32_RLC_NO_KIQ(req, inv_req, hub_ip); - - /* Wait for ACK with a delay.*/ - for (i = 0; i < adev->usec_timeout; i++) { - tmp = RREG32_RLC_NO_KIQ(ack, hub_ip); - tmp &= 1 << vmid; - if (tmp) - break; - - udelay(1); - } - - /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ - if (use_semaphore) - WREG32_RLC_NO_KIQ(sem, 0, hub_ip); - - /* Issue additional private vm invalidation to MMHUB */ - if ((vmhub != AMDGPU_GFXHUB(0)) && - (hub->vm_l2_bank_select_reserved_cid2) && - !amdgpu_sriov_vf(adev)) { - inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); - /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ - inv_req |= (1 << 25); - /* Issue private invalidation */ - WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); - /* Read back to ensure invalidation is done*/ - RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); - } - - spin_unlock(&adev->gmc.invalidate_lock); - - if (hub_ip == GC_HWIP) - amdgpu_gfx_off_ctrl(adev, true); - - if (i >= adev->usec_timeout) - dev_err(adev->dev, "Timeout waiting for VM flush ACK!\n"); -} - -/** - * gmc_v11_0_flush_gpu_tlb_pasid - tlb flush via pasid - * - * @adev: amdgpu_device pointer - * @pasid: pasid to be flush - * @flush_type: the flush type - * @all_hub: flush all hubs - * @inst: is used to select which instance of KIQ to use for the invalidation - * - * Flush the TLB for the requested pasid. - */ -static void gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, - uint16_t pasid, uint32_t flush_type, - bool all_hub, uint32_t inst) -{ - uint16_t queried; - int vmid, i; - - for (vmid = 1; vmid < 16; vmid++) { - bool valid; - - valid = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid, 0, - &queried); - if (!valid || queried != pasid) - continue; - - if (all_hub) { - for_each_set_bit(i, adev->vmhubs_mask, - AMDGPU_MAX_VMHUBS) - gmc_v11_0_flush_gpu_tlb(adev, vmid, i, - flush_type); - } else { - gmc_v11_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), - flush_type); - } - } -} - -static uint64_t gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, - unsigned int vmid, uint64_t pd_addr) -{ - bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); - struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; - uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); - unsigned int eng = ring->vm_inv_eng; - - /* - * It may lose gpuvm invalidate acknowldege state across power-gating - * off cycle, add semaphore acquire before invalidation and semaphore - * release after invalidation to avoid entering power gated state - * to WA the Issue - */ - - /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ - if (use_semaphore) - /* a read return value of 1 means semaphore acuqire */ - amdgpu_ring_emit_reg_wait(ring, - hub->vm_inv_eng0_sem + - hub->eng_distance * eng, 0x1, 0x1); - - amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + - (hub->ctx_addr_distance * vmid), - lower_32_bits(pd_addr)); - - amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + - (hub->ctx_addr_distance * vmid), - upper_32_bits(pd_addr)); - - amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + - hub->eng_distance * eng, - hub->vm_inv_eng0_ack + - hub->eng_distance * eng, - req, 1 << vmid); - - /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ - if (use_semaphore) - /* - * add semaphore release after invalidation, - * write with 0 means semaphore release - */ - amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + - hub->eng_distance * eng, 0); - - return pd_addr; -} - static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, unsigned int pasid) { @@ -543,9 +347,9 @@ static unsigned int gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev) } static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = { - .flush_gpu_tlb = gmc_v11_0_flush_gpu_tlb, - .flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid, - .emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb, + .flush_gpu_tlb = amdgpu_gmc_flush_gpu_tlb_helper, + .flush_gpu_tlb_pasid = amdgpu_gmc_flush_gpu_tlb_pasid_helper, + .emit_flush_gpu_tlb = amdgpu_gmc_emit_flush_gpu_tlb_helper, .emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping, .get_vmid_pasid_mapping_info = gmc_v11_0_get_vmid_pasid_mapping_info, .use_invalidate_semaphore = gmc_v11_0_use_invalidate_semaphore, @@ -935,7 +739,7 @@ static int gmc_v11_0_gart_enable(struct amdgpu_device *adev) value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; adev->mmhub.funcs->set_fault_enable_default(adev, value); - gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); + adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); drm_info(adev_to_drm(adev), "PCIE GART of %uM enabled (table at 0x%016llX).\n", (unsigned int)(adev->gmc.gart_size >> 20), diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 4bb8c1e4f335b..842ea38347367 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -211,219 +211,6 @@ static bool gmc_v12_0_get_vmid_pasid_mapping_info( * by the amdgpu vm/hsa code. */ -static void gmc_v12_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, - unsigned int vmhub, uint32_t flush_type) -{ - bool use_semaphore = gmc_v12_0_use_invalidate_semaphore(adev, vmhub); - struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; - u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); - u32 tmp; - /* Use register 17 for GART */ - const unsigned eng = 17; - unsigned int i; - unsigned char hub_ip = 0; - - hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? - GC_HWIP : MMHUB_HWIP; - - spin_lock(&adev->gmc.invalidate_lock); - /* - * It may lose gpuvm invalidate acknowldege state across power-gating - * off cycle, add semaphore acquire before invalidation and semaphore - * release after invalidation to avoid entering power gated state - * to WA the Issue - */ - - /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ - if (use_semaphore) { - for (i = 0; i < adev->usec_timeout; i++) { - /* a read return value of 1 means semaphore acuqire */ - tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + - hub->eng_distance * eng, hub_ip); - if (tmp & 0x1) - break; - udelay(1); - } - - if (i >= adev->usec_timeout) - dev_err(adev->dev, - "Timeout waiting for sem acquire in VM flush!\n"); - } - - WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req, hub_ip); - - /* Wait for ACK with a delay.*/ - for (i = 0; i < adev->usec_timeout; i++) { - tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + - hub->eng_distance * eng, hub_ip); - tmp &= 1 << vmid; - if (tmp) - break; - - udelay(1); - } - - /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ - if (use_semaphore) - /* - * add semaphore release after invalidation, - * write with 0 means semaphore release - */ - WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + - hub->eng_distance * eng, 0, hub_ip); - - /* Issue additional private vm invalidation to MMHUB */ - if ((vmhub != AMDGPU_GFXHUB(0)) && - (hub->vm_l2_bank_select_reserved_cid2) && - !amdgpu_sriov_vf(adev)) { - inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); - /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ - inv_req |= (1 << 25); - /* Issue private invalidation */ - WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); - /* Read back to ensure invalidation is done*/ - RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); - } - - spin_unlock(&adev->gmc.invalidate_lock); - - if (i < adev->usec_timeout) - return; - - dev_err(adev->dev, "Timeout waiting for VM flush ACK!\n"); -} - -/** - * gmc_v12_0_flush_gpu_tlb - gart tlb flush callback - * - * @adev: amdgpu_device pointer - * @vmid: vm instance to flush - * @vmhub: which hub to flush - * @flush_type: the flush type - * - * Flush the TLB for the requested page table. - */ -static void gmc_v12_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, - uint32_t vmhub, uint32_t flush_type) -{ - if ((vmhub == AMDGPU_GFXHUB(0)) && !adev->gfx.is_poweron) - return; - - /* flush hdp cache */ - amdgpu_device_flush_hdp(adev, NULL); - - /* This is necessary for SRIOV as well as for GFXOFF to function - * properly under bare metal - */ - if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring[0].sched.ready) && - !adev->gmc.use_mmio_for_tlb_flush) { - struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; - const unsigned eng = 17; - u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); - u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; - u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; - - amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, - 1 << vmid, GET_INST(GC, 0)); - return; - } - - /* disabllow gfxoff when we invalidate */ - if (vmhub == AMDGPU_GFXHUB(0)) - amdgpu_gfx_off_ctrl(adev, false); - - gmc_v12_0_flush_vm_hub(adev, vmid, vmhub, 0); - - if (vmhub == AMDGPU_GFXHUB(0)) - amdgpu_gfx_off_ctrl(adev, true); -} - -/** - * gmc_v12_0_flush_gpu_tlb_pasid - tlb flush via pasid - * - * @adev: amdgpu_device pointer - * @pasid: pasid to be flush - * @flush_type: the flush type - * @all_hub: flush all hubs - * @inst: is used to select which instance of KIQ to use for the invalidation - * - * Flush the TLB for the requested pasid. - */ -static void gmc_v12_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, - uint16_t pasid, uint32_t flush_type, - bool all_hub, uint32_t inst) -{ - uint16_t queried; - int vmid, i; - - for (vmid = 1; vmid < 16; vmid++) { - bool valid; - - valid = gmc_v12_0_get_vmid_pasid_mapping_info(adev, vmid, 0, - &queried); - if (!valid || queried != pasid) - continue; - - if (all_hub) { - for_each_set_bit(i, adev->vmhubs_mask, - AMDGPU_MAX_VMHUBS) - gmc_v12_0_flush_gpu_tlb(adev, vmid, i, - flush_type); - } else { - gmc_v12_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), - flush_type); - } - } -} - -static uint64_t gmc_v12_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, - unsigned vmid, uint64_t pd_addr) -{ - bool use_semaphore = gmc_v12_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); - struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; - uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); - unsigned eng = ring->vm_inv_eng; - - /* - * It may lose gpuvm invalidate acknowldege state across power-gating - * off cycle, add semaphore acquire before invalidation and semaphore - * release after invalidation to avoid entering power gated state - * to WA the Issue - */ - - /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ - if (use_semaphore) - /* a read return value of 1 means semaphore acuqire */ - amdgpu_ring_emit_reg_wait(ring, - hub->vm_inv_eng0_sem + - hub->eng_distance * eng, 0x1, 0x1); - - amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + - (hub->ctx_addr_distance * vmid), - lower_32_bits(pd_addr)); - - amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + - (hub->ctx_addr_distance * vmid), - upper_32_bits(pd_addr)); - - amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + - hub->eng_distance * eng, - hub->vm_inv_eng0_ack + - hub->eng_distance * eng, - req, 1 << vmid); - - /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ - if (use_semaphore) - /* - * add semaphore release after invalidation, - * write with 0 means semaphore release - */ - amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + - hub->eng_distance * eng, 0); - - return pd_addr; -} - static void gmc_v12_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, unsigned pasid) { @@ -562,9 +349,9 @@ static unsigned int gmc_v12_0_get_dcc_alignment(struct amdgpu_device *adev) } static const struct amdgpu_gmc_funcs gmc_v12_0_gmc_funcs = { - .flush_gpu_tlb = gmc_v12_0_flush_gpu_tlb, - .flush_gpu_tlb_pasid = gmc_v12_0_flush_gpu_tlb_pasid, - .emit_flush_gpu_tlb = gmc_v12_0_emit_flush_gpu_tlb, + .flush_gpu_tlb = amdgpu_gmc_flush_gpu_tlb_helper, + .flush_gpu_tlb_pasid = amdgpu_gmc_flush_gpu_tlb_pasid_helper, + .emit_flush_gpu_tlb = amdgpu_gmc_emit_flush_gpu_tlb_helper, .emit_pasid_mapping = gmc_v12_0_emit_pasid_mapping, .get_vmid_pasid_mapping_info = gmc_v12_0_get_vmid_pasid_mapping_info, .use_invalidate_semaphore = gmc_v12_0_use_invalidate_semaphore, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c index 2c980dc02c262..b20088e841349 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c @@ -281,195 +281,6 @@ static bool gmc_v12_1_use_invalidate_semaphore(struct amdgpu_device *adev, (!amdgpu_sriov_vf(adev))); } -static void gmc_v12_1_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, - unsigned int vmhub, uint32_t flush_type) -{ - bool use_semaphore = gmc_v12_1_use_invalidate_semaphore(adev, vmhub); - struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; - u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); - u32 tmp; - /* Use register 17 for GART */ - const unsigned eng = 17; - unsigned int i; - unsigned char hub_ip = 0; - - hub_ip = (AMDGPU_IS_GFXHUB(vmhub)) ? - GC_HWIP : MMHUB_HWIP; - - spin_lock(&adev->gmc.invalidate_lock); - - if (use_semaphore) { - for (i = 0; i < adev->usec_timeout; i++) { - /* a read return value of 1 means semaphore acuqire */ - tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + hub->eng_distance * eng, hub_ip); - if (tmp & 0x1) - break; - udelay(1); - } - - if (i >= adev->usec_timeout) - DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); - } - - WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req, hub_ip); - - /* Wait for ACK with a delay.*/ - for (i = 0; i < adev->usec_timeout; i++) { - tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + - hub->eng_distance * eng, hub_ip); - tmp &= 1 << vmid; - if (tmp) - break; - - udelay(1); - } - - if (use_semaphore) - WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0, hub_ip); - - /* Issue additional private vm invalidation to MMHUB */ - if (!AMDGPU_IS_GFXHUB(vmhub) && - (hub->vm_l2_bank_select_reserved_cid2) && - !amdgpu_sriov_vf(adev)) { - inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); - /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ - inv_req |= (1 << 25); - /* Issue private invalidation */ - WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); - /* Read back to ensure invalidation is done*/ - RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); - } - - spin_unlock(&adev->gmc.invalidate_lock); - - if (i < adev->usec_timeout) - return; - - dev_err(adev->dev, "Timeout waiting for VM flush ACK!\n"); -} - -/** - * gmc_v12_1_flush_gpu_tlb - gart tlb flush callback - * - * @adev: amdgpu_device pointer - * @vmid: vm instance to flush - * @vmhub: which hub to flush - * @flush_type: the flush type - * - * Flush the TLB for the requested page table. - */ -static void gmc_v12_1_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, - uint32_t vmhub, uint32_t flush_type) -{ - u32 inst; - - if (AMDGPU_IS_GFXHUB(vmhub) && - !adev->gfx.is_poweron) - return; - - if (vmhub >= AMDGPU_MMHUB0(0)) - inst = 0; - else - inst = vmhub; - - /* This is necessary for SRIOV as well as for GFXOFF to function - * properly under bare metal - */ - if ((adev->gfx.kiq[inst].ring.sched.ready || - adev->mes.ring[MES_PIPE_INST(inst, 0)].sched.ready) && - !adev->gmc.use_mmio_for_tlb_flush) { - struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; - const unsigned eng = 17; - u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); - u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; - u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; - - amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, - 1 << vmid, inst); - return; - } - - gmc_v12_1_flush_vm_hub(adev, vmid, vmhub, 0); - return; -} - -/** - * gmc_v12_1_flush_gpu_tlb_pasid - tlb flush via pasid - * - * @adev: amdgpu_device pointer - * @pasid: pasid to be flush - * @flush_type: the flush type - * @all_hub: flush all hubs - * @inst: is used to select which instance of KIQ to use for the invalidation - * - * Flush the TLB for the requested pasid. - */ -static void gmc_v12_1_flush_gpu_tlb_pasid(struct amdgpu_device *adev, - uint16_t pasid, uint32_t flush_type, - bool all_hub, uint32_t inst) -{ - uint16_t queried; - int vmid, i; - - for (vmid = 1; vmid < 16; vmid++) { - bool valid; - - valid = gmc_v12_1_get_vmid_pasid_mapping_info(adev, vmid, inst, - &queried); - if (!valid || queried != pasid) - continue; - - if (all_hub) { - for_each_set_bit(i, adev->vmhubs_mask, - AMDGPU_MAX_VMHUBS) - gmc_v12_1_flush_gpu_tlb(adev, vmid, i, - flush_type); - } else { - gmc_v12_1_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(inst), - flush_type); - } - } -} - -static uint64_t gmc_v12_1_emit_flush_gpu_tlb(struct amdgpu_ring *ring, - unsigned vmid, uint64_t pd_addr) -{ - bool use_semaphore = gmc_v12_1_use_invalidate_semaphore(ring->adev, ring->vm_hub); - struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; - uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); - unsigned eng = ring->vm_inv_eng; - - if (use_semaphore) - /* a read return value of 1 means semaphore acuqire */ - amdgpu_ring_emit_reg_wait(ring, - hub->vm_inv_eng0_sem + - hub->eng_distance * eng, 0x1, 0x1); - - amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + - (hub->ctx_addr_distance * vmid), - lower_32_bits(pd_addr)); - - amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + - (hub->ctx_addr_distance * vmid), - upper_32_bits(pd_addr)); - - amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + - hub->eng_distance * eng, - hub->vm_inv_eng0_ack + - hub->eng_distance * eng, - req, 1 << vmid); - - if (use_semaphore) - /* - * add semaphore release after invalidation, - * write with 0 means semaphore release - */ - amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + - hub->eng_distance * eng, 0); - - return pd_addr; -} - static void gmc_v12_1_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, unsigned pasid) { @@ -636,9 +447,9 @@ static void gmc_v12_1_get_vm_pte(struct amdgpu_device *adev, } static const struct amdgpu_gmc_funcs gmc_v12_1_gmc_funcs = { - .flush_gpu_tlb = gmc_v12_1_flush_gpu_tlb, - .flush_gpu_tlb_pasid = gmc_v12_1_flush_gpu_tlb_pasid, - .emit_flush_gpu_tlb = gmc_v12_1_emit_flush_gpu_tlb, + .flush_gpu_tlb = amdgpu_gmc_flush_gpu_tlb_helper, + .flush_gpu_tlb_pasid = amdgpu_gmc_flush_gpu_tlb_pasid_helper, + .emit_flush_gpu_tlb = amdgpu_gmc_emit_flush_gpu_tlb_helper, .emit_pasid_mapping = gmc_v12_1_emit_pasid_mapping, .get_vmid_pasid_mapping_info = gmc_v12_1_get_vmid_pasid_mapping_info, .use_invalidate_semaphore = gmc_v12_1_use_invalidate_semaphore, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 2b359c56f8d44..97a0d5b1a974c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -887,94 +887,6 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, DRM_ERROR("Timeout waiting for VM flush ACK!\n"); } -/** - * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid - * - * @adev: amdgpu_device pointer - * @pasid: pasid to be flush - * @flush_type: the flush type - * @all_hub: flush all hubs - * @inst: is used to select which instance of KIQ to use for the invalidation - * - * Flush the TLB for the requested pasid. - */ -static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, - uint16_t pasid, uint32_t flush_type, - bool all_hub, uint32_t inst) -{ - uint16_t queried; - int i, vmid; - - for (vmid = 1; vmid < 16; vmid++) { - bool valid; - - valid = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, - inst, &queried); - if (!valid || queried != pasid) - continue; - - if (all_hub) { - for_each_set_bit(i, adev->vmhubs_mask, - AMDGPU_MAX_VMHUBS) - gmc_v9_0_flush_gpu_tlb(adev, vmid, i, - flush_type); - } else { - gmc_v9_0_flush_gpu_tlb(adev, vmid, - AMDGPU_GFXHUB(0), - flush_type); - } - } -} - -static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, - unsigned int vmid, uint64_t pd_addr) -{ - bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); - struct amdgpu_device *adev = ring->adev; - struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub]; - uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); - unsigned int eng = ring->vm_inv_eng; - - /* - * It may lose gpuvm invalidate acknowldege state across power-gating - * off cycle, add semaphore acquire before invalidation and semaphore - * release after invalidation to avoid entering power gated state - * to WA the Issue - */ - - /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ - if (use_semaphore) - /* a read return value of 1 means semaphore acuqire */ - amdgpu_ring_emit_reg_wait(ring, - hub->vm_inv_eng0_sem + - hub->eng_distance * eng, 0x1, 0x1); - - amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + - (hub->ctx_addr_distance * vmid), - lower_32_bits(pd_addr)); - - amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + - (hub->ctx_addr_distance * vmid), - upper_32_bits(pd_addr)); - - amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + - hub->eng_distance * eng, - hub->vm_inv_eng0_ack + - hub->eng_distance * eng, - req, 1 << vmid); - - /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ - if (use_semaphore) - /* - * add semaphore release after invalidation, - * write with 0 means semaphore release - */ - amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + - hub->eng_distance * eng, 0); - - return pd_addr; -} - static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, unsigned int pasid) { @@ -1319,8 +1231,8 @@ static bool gmc_v9_0_need_reset_on_init(struct amdgpu_device *adev) static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, - .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, - .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, + .flush_gpu_tlb_pasid = amdgpu_gmc_flush_gpu_tlb_pasid_helper, + .emit_flush_gpu_tlb = amdgpu_gmc_emit_flush_gpu_tlb_helper, .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, .get_vmid_pasid_mapping_info = gmc_v9_0_get_atc_vmid_pasid_mapping_info, .use_invalidate_semaphore = gmc_v9_0_use_invalidate_semaphore, -- 2.55.0
