This prepares the code for implementing recovery for SI DMA. Reorganize the SI DMA code so that the functions that are responsible for managing the DMA engines take an instance ID as an argument.
This makes it possible to manage the two DMA instances independently of each other, which will enable us to also use these functions to implement resetting and recovering them independently. Signed-off-by: Timur Kristóf <[email protected]> --- drivers/gpu/drm/amd/amdgpu/si_dma.c | 97 ++++++++++++++--------------- 1 file changed, 47 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 31ab701d45d3..483a0cfb7c8f 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -125,74 +125,64 @@ static void si_dma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0, 0)); } -static void si_dma_stop(struct amdgpu_device *adev) +static void si_dma_stop(struct amdgpu_device *adev, const u32 instance_id) { + const u32 reg_offset = sdma_offsets[instance_id]; u32 rb_cntl; - unsigned i; - for (i = 0; i < adev->sdma.num_instances; i++) { - /* dma0 */ - rb_cntl = RREG32(mmDMA_GFX_RB_CNTL + sdma_offsets[i]); - rb_cntl &= ~DMA_GFX_RB_CNTL__RB_ENABLE_MASK; - WREG32(mmDMA_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); - } + rb_cntl = RREG32(mmDMA_GFX_RB_CNTL + reg_offset); + rb_cntl &= ~DMA_GFX_RB_CNTL__RB_ENABLE_MASK; + WREG32(mmDMA_GFX_RB_CNTL + reg_offset, rb_cntl); } -static int si_dma_start(struct amdgpu_device *adev) +static int si_dma_start(struct amdgpu_device *adev, const u32 instance_id) { - struct amdgpu_ring *ring; + struct amdgpu_ring *ring = &adev->sdma.instance[instance_id].ring; + const u32 reg_offset = sdma_offsets[instance_id]; u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; - int i, r; uint64_t rptr_addr; - for (i = 0; i < adev->sdma.num_instances; i++) { - ring = &adev->sdma.instance[i].ring; - - WREG32(mmDMA_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); - WREG32(mmDMA_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); + WREG32(mmDMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); + WREG32(mmDMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); - /* Set ring buffer size in dwords */ - rb_bufsz = order_base_2(ring->ring_size / 4); - rb_cntl = rb_bufsz << 1; + /* Set ring buffer size in dwords */ + rb_bufsz = order_base_2(ring->ring_size / 4); + rb_cntl = rb_bufsz << 1; #ifdef __BIG_ENDIAN - rb_cntl |= DMA_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | DMA_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK; + rb_cntl |= DMA_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | + DMA_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK; #endif - WREG32(mmDMA_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); + WREG32(mmDMA_GFX_RB_CNTL + reg_offset, rb_cntl); - /* Initialize the ring buffer's read and write pointers */ - WREG32(mmDMA_GFX_RB_RPTR + sdma_offsets[i], 0); - WREG32(mmDMA_GFX_RB_WPTR + sdma_offsets[i], 0); + /* Initialize the ring buffer's read and write pointers */ + WREG32(mmDMA_GFX_RB_RPTR + reg_offset, 0); + WREG32(mmDMA_GFX_RB_WPTR + reg_offset, 0); - rptr_addr = ring->rptr_gpu_addr; + rptr_addr = ring->rptr_gpu_addr; - WREG32(mmDMA_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr)); - WREG32(mmDMA_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) & 0xFF); + WREG32(mmDMA_GFX_RB_RPTR_ADDR_LO + reg_offset, lower_32_bits(rptr_addr)); + WREG32(mmDMA_GFX_RB_RPTR_ADDR_HI + reg_offset, upper_32_bits(rptr_addr) & 0xFF); - rb_cntl |= DMA_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; + rb_cntl |= DMA_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; - WREG32(mmDMA_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); + WREG32(mmDMA_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8); - /* enable DMA IBs */ - ib_cntl = DMA_GFX_IB_CNTL__IB_ENABLE_MASK | DMA_GFX_IB_CNTL__CMD_VMID_FORCE_MASK; + /* enable DMA IBs */ + ib_cntl = DMA_GFX_IB_CNTL__IB_ENABLE_MASK | DMA_GFX_IB_CNTL__CMD_VMID_FORCE_MASK; #ifdef __BIG_ENDIAN - ib_cntl |= DMA_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK; + ib_cntl |= DMA_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK; #endif - WREG32(mmDMA_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); - - dma_cntl = RREG32(mmDMA_CNTL + sdma_offsets[i]); - dma_cntl &= ~DMA_CNTL__CTXEMPTY_INT_ENABLE_MASK; - WREG32(mmDMA_CNTL + sdma_offsets[i], dma_cntl); + WREG32(mmDMA_GFX_IB_CNTL + reg_offset, ib_cntl); - ring->wptr = 0; - WREG32(mmDMA_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); - WREG32(mmDMA_GFX_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_GFX_RB_CNTL__RB_ENABLE_MASK); + dma_cntl = RREG32(mmDMA_CNTL + reg_offset); + dma_cntl &= ~DMA_CNTL__CTXEMPTY_INT_ENABLE_MASK; + WREG32(mmDMA_CNTL + reg_offset, dma_cntl); - r = amdgpu_ring_test_helper(ring); - if (r) - return r; - } + ring->wptr = 0; + WREG32(mmDMA_GFX_RB_WPTR + reg_offset, ring->wptr << 2); + WREG32(mmDMA_GFX_RB_CNTL + reg_offset, rb_cntl | DMA_GFX_RB_CNTL__RB_ENABLE_MASK); - return 0; + return amdgpu_ring_test_helper(ring); } /** @@ -548,11 +538,14 @@ static int si_dma_sw_fini(struct amdgpu_ip_block *ip_block) static int si_dma_hw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; - int r; + int i, r; + + for (i = 0; i < adev->sdma.num_instances; ++i) { + r = si_dma_start(adev, i); + if (r) + return r; + } - r = si_dma_start(adev); - if (r) - return r; si_dma_set_buffer_funcs(adev); return 0; @@ -560,7 +553,11 @@ static int si_dma_hw_init(struct amdgpu_ip_block *ip_block) static int si_dma_hw_fini(struct amdgpu_ip_block *ip_block) { - si_dma_stop(ip_block->adev); + struct amdgpu_device *adev = ip_block->adev; + int i; + + for (i = 0; i < adev->sdma.num_instances; ++i) + si_dma_stop(adev, i); return 0; } -- 2.55.0
