Refactor golden registers initialization to take the SDMA engine instance ID as an argument and only program the golden registers for one SDMA engine at once.
Signed-off-by: Timur Kristóf <[email protected]> --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 237 +++++++++++++++++++------ 1 file changed, 182 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 259857596cfd..ef9058dd1082 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -132,7 +132,7 @@ static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev); -static const struct soc15_reg_golden golden_settings_sdma_4[] = { +static const struct soc15_reg_golden golden_settings_v4_0_sdma0[] = { SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), @@ -146,6 +146,9 @@ static const struct soc15_reg_golden golden_settings_sdma_4[] = { SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), +}; + +static const struct soc15_reg_golden golden_settings_v4_0_sdma1[] = { SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), @@ -160,27 +163,33 @@ static const struct soc15_reg_golden golden_settings_sdma_4[] = { SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) }; -static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { +static const struct soc15_reg_golden golden_settings_vg10_sdma0[] = { SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), +}; + +static const struct soc15_reg_golden golden_settings_vg10_sdma1[] = { SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), }; -static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { +static const struct soc15_reg_golden golden_settings_vg12_sdma0[] = { SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), +}; + +static const struct soc15_reg_golden golden_settings_vg12_sdma1[] = { SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), }; -static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { +static const struct soc15_reg_golden golden_settings_v4_1_sdma0[] = { SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), @@ -194,12 +203,11 @@ static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) }; -static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { +static const struct soc15_reg_golden golden_settings_v4_2_sdma0_init[] = { SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), }; -static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = -{ +static const struct soc15_reg_golden golden_settings_v4_2_sdma0[] = { SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), @@ -229,7 +237,7 @@ static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), }; -static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { +static const struct soc15_reg_golden golden_settings_v4_2_sdma1[] = { SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), @@ -259,73 +267,103 @@ static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), }; -static const struct soc15_reg_golden golden_settings_sdma_rv1[] = -{ +static const struct soc15_reg_golden golden_settings_rv1_sdma0[] = { SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) }; -static const struct soc15_reg_golden golden_settings_sdma_rv2[] = -{ +static const struct soc15_reg_golden golden_settings_rv2_sdma0[] = { SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) }; -static const struct soc15_reg_golden golden_settings_sdma_arct[] = -{ +static const struct soc15_reg_golden golden_settings_arct_sdma0[] = { SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), +}; + +static const struct soc15_reg_golden golden_settings_arct_sdma1[] = { SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), +}; + +static const struct soc15_reg_golden golden_settings_arct_sdma2[] = { SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07), SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), +}; + +static const struct soc15_reg_golden golden_settings_arct_sdma3[] = { SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07), SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), +}; + +static const struct soc15_reg_golden golden_settings_arct_sdma4[] = { SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07), SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), +}; + +static const struct soc15_reg_golden golden_settings_arct_sdma5[] = { SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07), SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), +}; + +static const struct soc15_reg_golden golden_settings_arct_sdma6[] = { SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07), SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), +}; + +static const struct soc15_reg_golden golden_settings_arct_sdma7[] = { SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07), SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001) }; -static const struct soc15_reg_golden golden_settings_sdma_aldebaran[] = { +static const struct soc15_reg_golden golden_settings_aldebaran_sdma0[] = { SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), +}; + +static const struct soc15_reg_golden golden_settings_aldebaran_sdma1[] = { SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), +}; + +static const struct soc15_reg_golden golden_settings_aldebaran_sdma2[] = { SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), +}; + +static const struct soc15_reg_golden golden_settings_aldebaran_sdma3[] = { SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), +}; + +static const struct soc15_reg_golden golden_settings_aldebaran_sdma4[] = { SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), }; -static const struct soc15_reg_golden golden_settings_sdma_4_3[] = { +static const struct soc15_reg_golden golden_settings_v4_3_sdma0[] = { SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), @@ -513,64 +551,155 @@ static int sdma_v4_0_irq_id_to_seq(unsigned client_id) return -EINVAL; } -static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) +static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev, const u32 instance_id) { switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { case IP_VERSION(4, 0, 0): - soc15_program_register_sequence(adev, - golden_settings_sdma_4, - ARRAY_SIZE(golden_settings_sdma_4)); - soc15_program_register_sequence(adev, - golden_settings_sdma_vg10, - ARRAY_SIZE(golden_settings_sdma_vg10)); + if (instance_id == 0) { + soc15_program_register_sequence( + adev, + golden_settings_v4_0_sdma0, + ARRAY_SIZE(golden_settings_v4_0_sdma0)); + soc15_program_register_sequence( + adev, + golden_settings_vg10_sdma0, + ARRAY_SIZE(golden_settings_vg10_sdma0)); + } else if (instance_id == 1) { + soc15_program_register_sequence( + adev, + golden_settings_v4_0_sdma1, + ARRAY_SIZE(golden_settings_v4_0_sdma1)); + soc15_program_register_sequence( + adev, + golden_settings_vg10_sdma1, + ARRAY_SIZE(golden_settings_vg10_sdma1)); + } break; case IP_VERSION(4, 0, 1): - soc15_program_register_sequence(adev, - golden_settings_sdma_4, - ARRAY_SIZE(golden_settings_sdma_4)); - soc15_program_register_sequence(adev, - golden_settings_sdma_vg12, - ARRAY_SIZE(golden_settings_sdma_vg12)); + if (instance_id == 0) { + soc15_program_register_sequence( + adev, + golden_settings_v4_0_sdma0, + ARRAY_SIZE(golden_settings_v4_0_sdma0)); + soc15_program_register_sequence( + adev, + golden_settings_vg12_sdma0, + ARRAY_SIZE(golden_settings_vg12_sdma0)); + } else if (instance_id == 1) { + soc15_program_register_sequence( + adev, + golden_settings_v4_0_sdma1, + ARRAY_SIZE(golden_settings_v4_0_sdma1)); + soc15_program_register_sequence( + adev, + golden_settings_vg12_sdma1, + ARRAY_SIZE(golden_settings_vg12_sdma1)); + } break; case IP_VERSION(4, 2, 0): - soc15_program_register_sequence(adev, - golden_settings_sdma0_4_2_init, - ARRAY_SIZE(golden_settings_sdma0_4_2_init)); - soc15_program_register_sequence(adev, - golden_settings_sdma0_4_2, - ARRAY_SIZE(golden_settings_sdma0_4_2)); - soc15_program_register_sequence(adev, - golden_settings_sdma1_4_2, - ARRAY_SIZE(golden_settings_sdma1_4_2)); + if (instance_id == 0) { + soc15_program_register_sequence( + adev, + golden_settings_v4_2_sdma0_init, + ARRAY_SIZE(golden_settings_v4_2_sdma0_init)); + soc15_program_register_sequence( + adev, + golden_settings_v4_2_sdma0, + ARRAY_SIZE(golden_settings_v4_2_sdma0)); + } else if (instance_id == 1) { + soc15_program_register_sequence( + adev, + golden_settings_v4_2_sdma1, + ARRAY_SIZE(golden_settings_v4_2_sdma1)); + } break; case IP_VERSION(4, 2, 2): - soc15_program_register_sequence(adev, - golden_settings_sdma_arct, - ARRAY_SIZE(golden_settings_sdma_arct)); + if (instance_id == 0) + soc15_program_register_sequence( + adev, + golden_settings_arct_sdma0, + ARRAY_SIZE(golden_settings_arct_sdma0)); + else if (instance_id == 1) + soc15_program_register_sequence( + adev, + golden_settings_arct_sdma1, + ARRAY_SIZE(golden_settings_arct_sdma1)); + else if (instance_id == 2) + soc15_program_register_sequence( + adev, + golden_settings_arct_sdma2, + ARRAY_SIZE(golden_settings_arct_sdma2)); + else if (instance_id == 3) + soc15_program_register_sequence( + adev, + golden_settings_arct_sdma3, + ARRAY_SIZE(golden_settings_arct_sdma3)); + else if (instance_id == 4) + soc15_program_register_sequence( + adev, + golden_settings_arct_sdma4, + ARRAY_SIZE(golden_settings_arct_sdma4)); + else if (instance_id == 5) + soc15_program_register_sequence( + adev, + golden_settings_arct_sdma5, + ARRAY_SIZE(golden_settings_arct_sdma5)); + else if (instance_id == 6) + soc15_program_register_sequence( + adev, + golden_settings_arct_sdma6, + ARRAY_SIZE(golden_settings_arct_sdma6)); + else if (instance_id == 7) + soc15_program_register_sequence( + adev, + golden_settings_arct_sdma7, + ARRAY_SIZE(golden_settings_arct_sdma7)); break; case IP_VERSION(4, 4, 0): - soc15_program_register_sequence(adev, - golden_settings_sdma_aldebaran, - ARRAY_SIZE(golden_settings_sdma_aldebaran)); + if (instance_id == 0) + soc15_program_register_sequence( + adev, + golden_settings_aldebaran_sdma0, + ARRAY_SIZE(golden_settings_aldebaran_sdma0)); + else if (instance_id == 1) + soc15_program_register_sequence( + adev, + golden_settings_aldebaran_sdma1, + ARRAY_SIZE(golden_settings_aldebaran_sdma1)); + else if (instance_id == 2) + soc15_program_register_sequence( + adev, + golden_settings_aldebaran_sdma2, + ARRAY_SIZE(golden_settings_aldebaran_sdma2)); + else if (instance_id == 3) + soc15_program_register_sequence( + adev, + golden_settings_aldebaran_sdma3, + ARRAY_SIZE(golden_settings_aldebaran_sdma3)); + else if (instance_id == 4) + soc15_program_register_sequence( + adev, + golden_settings_aldebaran_sdma4, + ARRAY_SIZE(golden_settings_aldebaran_sdma4)); break; case IP_VERSION(4, 1, 0): case IP_VERSION(4, 1, 1): soc15_program_register_sequence(adev, - golden_settings_sdma_4_1, - ARRAY_SIZE(golden_settings_sdma_4_1)); + golden_settings_v4_1_sdma0, + ARRAY_SIZE(golden_settings_v4_1_sdma0)); if (adev->apu_flags & AMD_APU_IS_RAVEN2) soc15_program_register_sequence(adev, - golden_settings_sdma_rv2, - ARRAY_SIZE(golden_settings_sdma_rv2)); + golden_settings_rv2_sdma0, + ARRAY_SIZE(golden_settings_rv2_sdma0)); else soc15_program_register_sequence(adev, - golden_settings_sdma_rv1, - ARRAY_SIZE(golden_settings_sdma_rv1)); + golden_settings_rv1_sdma0, + ARRAY_SIZE(golden_settings_rv1_sdma0)); break; case IP_VERSION(4, 1, 2): soc15_program_register_sequence(adev, - golden_settings_sdma_4_3, - ARRAY_SIZE(golden_settings_sdma_4_3)); + golden_settings_v4_3_sdma0, + ARRAY_SIZE(golden_settings_v4_3_sdma0)); break; default: break; @@ -1353,6 +1482,7 @@ static int sdma_v4_0_start(struct amdgpu_device *adev, const u32 instance_id) sdma_v4_0_ctx_switch_enable(adev, instance_id, false); sdma_v4_0_enable(adev, instance_id, false); } else { + sdma_v4_0_init_golden_registers(adev, instance_id); if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { r = sdma_v4_0_load_microcode(adev, instance_id); @@ -1941,9 +2071,6 @@ static int sdma_v4_0_hw_init(struct amdgpu_ip_block *ip_block) if (adev->flags & AMD_IS_APU) amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false, 0); - if (!amdgpu_sriov_vf(adev)) - sdma_v4_0_init_golden_registers(adev); - for (i = 0; i < adev->sdma.num_instances; ++i) { r = sdma_v4_0_start(adev, i); if (r) -- 2.55.0
