From: Yi-Ling Chen <[email protected]> [Why] Disable FEC for certain panels.
[How] To align FEC HW/SW status when enabling the option. Reviewed-by: Aric Cyr <[email protected]> Signed-off-by: Yi-Ling Chen <[email protected]> Signed-off-by: Chenyu Chen <[email protected]> --- drivers/gpu/drm/amd/display/dc/core/dc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 8e8d221c2bc5..ab192291ed52 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1870,6 +1870,12 @@ bool dc_validate_boot_timing(const struct dc *dc, return false; } + if (sink->edid_caps.panel_patch.disable_fec && + (link->fec_state == dc_link_fec_enabled)) { + DC_LOG_DEBUG("boot timing validation failed due to FEC WA & FEC HW is active\n"); + return false; + } + /* Check for enabled DIG to identify enabled display */ if (!link->link_enc->funcs->is_dig_enabled(link->link_enc)) { DC_LOG_DEBUG("boot timing validation failed due to disabled DIG\n"); -- 2.43.0
