From: Piotr Maziarz <[email protected]> [Why] UT mirror headers still declared the old prototypes and hwss_gtest still called the callback directly. Separately, the divide by param.pixel_clk_khz used to sit after hubp401_cursor_set_position()'s "curs_attr.address == 0" early return; hoisting the math into the builder moved it ahead of that guard, so it now traps on streams with no timing programmed.
[How] Guard the dst_x_offset block with "if (param.pixel_clk_khz)" Route the test through hwss_program_cursor_position(). Update dc_hwss_ut.h / dc_hwseq_ut.h and the BLS docs to the new signatures. Move the pos/param declarations to the top of the loop body. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Piotr Maziarz <[email protected]> Signed-off-by: George Zhang <[email protected]> --- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 6 ++--- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 25 +++++++++++-------- 2 files changed, 17 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 3bc0362d9dc0..0a7408692cbe 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -1396,6 +1396,9 @@ void hwss_build_fast_sequence(struct dc *dc, struct pipe_ctx *cursor_pipe_to_program = NULL; for (i = 0; i < MAX_PIPES; i++) { + struct dc_cursor_position pos; + struct dc_cursor_mi_param param; + current_pipe = &context->res_ctx.pipe_ctx[i]; if (current_pipe->stream != stream || @@ -1419,9 +1422,6 @@ void hwss_build_fast_sequence(struct dc *dc, } } - struct dc_cursor_position pos; - struct dc_cursor_mi_param param; - dc->hwseq->funcs.build_cursor_position(current_pipe, &pos, ¶m); block_sequence[*num_steps].params.set_cursor_position_params.dc = dc; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 8fd60ed7669b..37b699c69144 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1233,20 +1233,23 @@ void dcn401_build_cursor_position(struct pipe_ctx *pipe_ctx, ASSERT(!pos_cpy.enable || pos_cpy.x_hotspot == 0); } - dst_x_offset = x_pos_viewport - x_hot_viewport * - (1 + hubp->curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION); - dst_x_offset = (dst_x_offset >= 0) ? dst_x_offset : 0; - dst_x_offset *= param.ref_clk_khz; - dst_x_offset /= param.pixel_clk_khz; + /* pixel_clk_khz is 0 when no timing is programmed on the stream */ + if (param.pixel_clk_khz) { + dst_x_offset = x_pos_viewport - x_hot_viewport * + (1 + hubp->curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION); + dst_x_offset = (dst_x_offset >= 0) ? dst_x_offset : 0; + dst_x_offset *= param.ref_clk_khz; + dst_x_offset /= param.pixel_clk_khz; - ASSERT(param.h_scale_ratio.value); + ASSERT(param.h_scale_ratio.value); - if (param.h_scale_ratio.value) - dst_x_offset = dc_fixpt_floor(dc_fixpt_div( - dc_fixpt_from_int(dst_x_offset), - param.h_scale_ratio)); + if (param.h_scale_ratio.value) + dst_x_offset = dc_fixpt_floor(dc_fixpt_div( + dc_fixpt_from_int(dst_x_offset), + param.h_scale_ratio)); - param.dst_x_offset = dst_x_offset; + param.dst_x_offset = dst_x_offset; + } /* Cursor rectangle cache origin: derived from the final cursor position * minus hotspot, clamped to 0, offset by the recout origin. Precompute -- 2.55.0
