From: Nicholas Kazlauskas <[email protected]> [Why] Inbox1 was previously being used for cursor and DIG locking with DMUB doing the relevant programming on behalf of driver.
With the Inbox0 lock the driver is expected to do the programming itself and the Inbox0 lock acts as nothing more than a SW mutex. There are still a few gaps in how Inbox1 was being leveraged in the cursor path that need to be addressed for Inbox0. [How] Add a `should_use_dmub_inbox0_lock_for_link` helper to help check if we support the Inbox0 locking infrastructure and we should be locking it if the specific link in question requires it. Reviewed-by: Nicholas Kazlauskas <[email protected]> Reviewend-by: George Zhang <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Zhikai Zhai <[email protected]> --- .../gpu/drm/amd/display/dc/core/dc_stream.c | 21 +++++++++++++++++++ .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 10 ++++++++- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 ++- 3 files changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 8d3aacc7b96c..88ac4a4cfd6e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -34,6 +34,7 @@ #include "dc_dmub_srv.h" #include "dc_state_priv.h" #include "dc_stream_priv.h" +#include "dce/dmub_hw_lock_mgr.h" #define DC_LOGGER dc->ctx->logger #ifndef MIN @@ -307,6 +308,7 @@ void program_cursor_attributes( struct resource_context *res_ctx; struct pipe_ctx *pipe_to_program = NULL; bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); + bool unlock_dmub = false; if (!stream) return; @@ -330,6 +332,12 @@ void program_cursor_attributes( pipe_ctx->plane_res.dpp, pipe_ctx->plane_res.hubp, top_pipe->pipe_idx); } else { + if (dc->hwss.dmub_hw_control_lock && pipe_ctx->stream && + should_use_dmub_inbox0_lock_for_link(dc, pipe_ctx->stream->link)) { + dc->hwss.dmub_hw_control_lock(dc, dc->current_state, true); + unlock_dmub = true; + } + dc->hwss.cursor_lock(dc, pipe_to_program, true); if (pipe_to_program->next_odm_pipe) dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, true); @@ -362,6 +370,9 @@ void program_cursor_attributes( dc->hwss.cursor_lock(dc, pipe_to_program, false); if (pipe_to_program->next_odm_pipe) dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, false); + + if (unlock_dmub) + dc->hwss.dmub_hw_control_lock(dc, dc->current_state, false); } } } @@ -481,6 +492,7 @@ void program_cursor_position( struct resource_context *res_ctx; struct pipe_ctx *pipe_to_program = NULL; bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); + bool unlock_dmub = false; if (!stream) return; @@ -508,6 +520,12 @@ void program_cursor_position( pipe_ctx->plane_res.dpp, pipe_ctx->plane_res.hubp, top_pipe->pipe_idx); } else { + if (dc->hwss.dmub_hw_control_lock && pipe_ctx->stream && + should_use_dmub_inbox0_lock_for_link(dc, pipe_ctx->stream->link)) { + dc->hwss.dmub_hw_control_lock(dc, dc->current_state, true); + unlock_dmub = true; + } + dc->hwss.cursor_lock(dc, pipe_to_program, true); } } @@ -535,6 +553,9 @@ void program_cursor_position( top_pipe->pipe_idx); } else { dc->hwss.cursor_lock(dc, pipe_to_program, false); + + if (unlock_dmub) + dc->hwss.dmub_hw_control_lock(dc, dc->current_state, false); } } } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c index 52673e2f504c..2ac1485a3438 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c @@ -36,6 +36,14 @@ static bool dmub_hw_lock_has_inbox0_lock(const struct dc *dc) dc->ctx->dmub_srv->dmub->meta_info.feature_bits.bits.inbox0_lock_support; } +static bool dmub_hw_lock_has_inbox0_lock_split(const struct dc *dc) +{ + return dc->ctx && dc->ctx->dmub_srv && + dc->hwss.dmub_hw_control_lock && + dc->hwss.dmub_hw_control_lock_fast && + dc->ctx->dmub_srv->dmub->meta_info.feature_bits.bits.inbox0_lock_split; +} + void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv, bool lock, union dmub_hw_lock_flags *hw_locks, @@ -121,5 +129,5 @@ bool should_use_dmub_inbox1_lock(const struct dc *dc, const struct dc_link *link bool should_use_dmub_inbox0_lock_for_link(const struct dc *dc, const struct dc_link *link) { - return dmub_hw_lock_has_inbox0_lock(dc) && dmub_hw_lock_mgr_does_link_require_lock(dc, link); + return dmub_hw_lock_has_inbox0_lock_split(dc) && dmub_hw_lock_mgr_does_link_require_lock(dc, link); } diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index ef576640de5b..af621b8552e1 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -1004,7 +1004,8 @@ union dmub_fw_meta_feature_bits { uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ uint32_t cursor_offload_v1_support: 1; /**< 1 supports cursor offload */ uint32_t inbox0_lock_support: 1; /**< 1 supports inbox0 lock mechanism */ - uint32_t reserved : 29; + uint32_t inbox0_lock_split: 1; /**< 1 supports inbox0 lock acquire/release split mechanism */ + uint32_t reserved : 28; } bits; /**< status bits */ uint32_t all; /**< 32-bit access to status bits */ }; -- 2.55.0
